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target/riscv: Implement mcountinhibit CSR
As per the privilege specification v1.11, mcountinhibit allows to start/stop a pmu counter selectively. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220620231603.2547260-6-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -275,6 +275,8 @@ struct CPUArchState {
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target_ulong scounteren;
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target_ulong mcounteren;
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target_ulong mcountinhibit;
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target_ulong sscratch;
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target_ulong mscratch;
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@ -367,6 +367,10 @@
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#define CSR_MHPMCOUNTER29 0xb1d
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#define CSR_MHPMCOUNTER30 0xb1e
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#define CSR_MHPMCOUNTER31 0xb1f
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/* Machine counter-inhibit register */
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#define CSR_MCOUNTINHIBIT 0x320
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#define CSR_MHPMEVENT3 0x323
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#define CSR_MHPMEVENT4 0x324
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#define CSR_MHPMEVENT5 0x325
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@ -1475,6 +1475,28 @@ static RISCVException write_mtvec(CPURISCVState *env, int csrno,
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return RISCV_EXCP_NONE;
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}
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static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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if (env->priv_ver < PRIV_VERSION_1_11_0) {
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return RISCV_EXCP_ILLEGAL_INST;
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}
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*val = env->mcountinhibit;
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return RISCV_EXCP_NONE;
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}
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static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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if (env->priv_ver < PRIV_VERSION_1_11_0) {
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return RISCV_EXCP_ILLEGAL_INST;
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}
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env->mcountinhibit = val;
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return RISCV_EXCP_NONE;
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}
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static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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@ -3745,6 +3767,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_zero },
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[CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_zero },
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[CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit,
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write_mcountinhibit },
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[CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
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[CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
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[CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero },
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@ -330,6 +330,7 @@ const VMStateDescription vmstate_riscv_cpu = {
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VMSTATE_UINTTL(env.siselect, RISCVCPU),
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VMSTATE_UINTTL(env.scounteren, RISCVCPU),
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VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
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VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
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VMSTATE_UINTTL(env.sscratch, RISCVCPU),
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VMSTATE_UINTTL(env.mscratch, RISCVCPU),
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VMSTATE_UINT64(env.mfromhost, RISCVCPU),
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