mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-09-06 18:05:37 +00:00
ppc/pnv: Remove PnvOCC::psi link
Use an anonymous output GPIO line to connect the OCC device with the PSIHB device and raise the appropriate PSI IRQ line depending on the processor model. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220323072846.1780212-4-clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
parent
c05aa1406b
commit
b0ae5c69e1
12
hw/ppc/pnv.c
12
hw/ppc/pnv.c
|
@ -1253,12 +1253,12 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
|
|||
}
|
||||
|
||||
/* Create the simplified OCC model */
|
||||
object_property_set_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi),
|
||||
&error_abort);
|
||||
if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) {
|
||||
return;
|
||||
}
|
||||
pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
|
||||
qdev_connect_gpio_out(DEVICE(&chip8->occ), 0,
|
||||
qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC));
|
||||
|
||||
/* OCC SRAM model */
|
||||
memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
|
||||
|
@ -1528,12 +1528,12 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
|
|||
(uint64_t) PNV9_LPCM_BASE(chip));
|
||||
|
||||
/* Create the simplified OCC model */
|
||||
object_property_set_link(OBJECT(&chip9->occ), "psi", OBJECT(&chip9->psi),
|
||||
&error_abort);
|
||||
if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) {
|
||||
return;
|
||||
}
|
||||
pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
|
||||
qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in(
|
||||
DEVICE(&chip9->psi), PSIHB9_IRQ_OCC));
|
||||
|
||||
/* OCC SRAM model */
|
||||
memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
|
||||
|
@ -1731,13 +1731,13 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
|
|||
(uint64_t) PNV10_LPCM_BASE(chip));
|
||||
|
||||
/* Create the simplified OCC model */
|
||||
object_property_set_link(OBJECT(&chip10->occ), "psi", OBJECT(&chip10->psi),
|
||||
&error_abort);
|
||||
if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) {
|
||||
return;
|
||||
}
|
||||
pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
|
||||
&chip10->occ.xscom_regs);
|
||||
qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in(
|
||||
DEVICE(&chip10->psi), PSIHB9_IRQ_OCC));
|
||||
|
||||
/* OCC SRAM model */
|
||||
memory_region_add_subregion(get_system_memory(),
|
||||
|
|
|
@ -21,6 +21,7 @@
|
|||
#include "qapi/error.h"
|
||||
#include "qemu/log.h"
|
||||
#include "qemu/module.h"
|
||||
#include "hw/irq.h"
|
||||
#include "hw/qdev-properties.h"
|
||||
#include "hw/ppc/pnv.h"
|
||||
#include "hw/ppc/pnv_xscom.h"
|
||||
|
@ -51,13 +52,12 @@
|
|||
static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val)
|
||||
{
|
||||
bool irq_state;
|
||||
PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
|
||||
|
||||
val &= 0xffff000000000000ull;
|
||||
|
||||
occ->occmisc = val;
|
||||
irq_state = !!(val >> 63);
|
||||
pnv_psi_irq_set(occ->psi, poc->psi_irq, irq_state);
|
||||
qemu_set_irq(occ->psi_irq, irq_state);
|
||||
}
|
||||
|
||||
static uint64_t pnv_occ_power8_xscom_read(void *opaque, hwaddr addr,
|
||||
|
@ -168,7 +168,6 @@ static void pnv_occ_power8_class_init(ObjectClass *klass, void *data)
|
|||
|
||||
poc->xscom_size = PNV_XSCOM_OCC_SIZE;
|
||||
poc->xscom_ops = &pnv_occ_power8_xscom_ops;
|
||||
poc->psi_irq = PSIHB_IRQ_OCC;
|
||||
}
|
||||
|
||||
static const TypeInfo pnv_occ_power8_type_info = {
|
||||
|
@ -241,7 +240,6 @@ static void pnv_occ_power9_class_init(ObjectClass *klass, void *data)
|
|||
dc->desc = "PowerNV OCC Controller (POWER9)";
|
||||
poc->xscom_size = PNV9_XSCOM_OCC_SIZE;
|
||||
poc->xscom_ops = &pnv_occ_power9_xscom_ops;
|
||||
poc->psi_irq = PSIHB9_IRQ_OCC;
|
||||
}
|
||||
|
||||
static const TypeInfo pnv_occ_power9_type_info = {
|
||||
|
@ -269,8 +267,6 @@ static void pnv_occ_realize(DeviceState *dev, Error **errp)
|
|||
PnvOCC *occ = PNV_OCC(dev);
|
||||
PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
|
||||
|
||||
assert(occ->psi);
|
||||
|
||||
occ->occmisc = 0;
|
||||
|
||||
/* XScom region for OCC registers */
|
||||
|
@ -281,12 +277,9 @@ static void pnv_occ_realize(DeviceState *dev, Error **errp)
|
|||
memory_region_init_io(&occ->sram_regs, OBJECT(dev), &pnv_occ_sram_ops,
|
||||
occ, "occ-common-area",
|
||||
PNV_OCC_SENSOR_DATA_BLOCK_SIZE);
|
||||
}
|
||||
|
||||
static Property pnv_occ_properties[] = {
|
||||
DEFINE_PROP_LINK("psi", PnvOCC, psi, TYPE_PNV_PSI, PnvPsi *),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
qdev_init_gpio_out(DEVICE(dev), &occ->psi_irq, 1);
|
||||
}
|
||||
|
||||
static void pnv_occ_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
|
@ -294,7 +287,6 @@ static void pnv_occ_class_init(ObjectClass *klass, void *data)
|
|||
|
||||
dc->realize = pnv_occ_realize;
|
||||
dc->desc = "PowerNV OCC Controller";
|
||||
device_class_set_props(dc, pnv_occ_properties);
|
||||
dc->user_creatable = false;
|
||||
}
|
||||
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* QEMU PowerPC PowerNV Emulation of a few OCC related registers
|
||||
*
|
||||
* Copyright (c) 2015-2017, IBM Corporation.
|
||||
* Copyright (c) 2015-2022, IBM Corporation.
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
|
@ -20,7 +20,6 @@
|
|||
#ifndef PPC_PNV_OCC_H
|
||||
#define PPC_PNV_OCC_H
|
||||
|
||||
#include "hw/ppc/pnv_psi.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_PNV_OCC "pnv-occ"
|
||||
|
@ -44,19 +43,17 @@ struct PnvOCC {
|
|||
/* OCC Misc interrupt */
|
||||
uint64_t occmisc;
|
||||
|
||||
PnvPsi *psi;
|
||||
qemu_irq psi_irq;
|
||||
|
||||
MemoryRegion xscom_regs;
|
||||
MemoryRegion sram_regs;
|
||||
};
|
||||
|
||||
|
||||
struct PnvOCCClass {
|
||||
DeviceClass parent_class;
|
||||
|
||||
int xscom_size;
|
||||
const MemoryRegionOps *xscom_ops;
|
||||
int psi_irq;
|
||||
};
|
||||
|
||||
#define PNV_OCC_SENSOR_DATA_BLOCK_BASE(i) \
|
||||
|
|
Loading…
Reference in a new issue