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tcg: initial mips support
Based on a patch from Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org> A few words about design choices: * Two registers, at and t0, are reserved for TCG internal use. They are useful for bswap and 64-bit ops. * Most ops supports a constant argument with value 0, which is actually mapped to the zero register. * While the at register is available for constant loading, ops only support a limited range of constants. TCG does a better job doing the register allocation and constant loading by itself. There are plenty of registers available anyway. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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configure
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configure
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@ -134,13 +134,15 @@ elif check_define _ARCH_PPC ; then
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else
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cpu="ppc"
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fi
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elif check_define __mips__ ; then
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cpu="mips"
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else
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cpu=`uname -m`
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fi
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target_list=""
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case "$cpu" in
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alpha|cris|ia64|m68k|microblaze|mips|mips64|ppc|ppc64|sparc64)
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alpha|cris|ia64|m68k|microblaze|ppc|ppc64|sparc64)
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cpu="$cpu"
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;;
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i386|i486|i586|i686|i86pc|BePC)
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@ -158,6 +160,9 @@ case "$cpu" in
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parisc|parisc64)
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cpu="hppa"
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;;
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mips*)
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cpu="mips"
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;;
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s390*)
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cpu="s390"
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;;
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1342
tcg/mips/tcg-target.c
Normal file
1342
tcg/mips/tcg-target.c
Normal file
File diff suppressed because it is too large
Load Diff
104
tcg/mips/tcg-target.h
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104
tcg/mips/tcg-target.h
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@ -0,0 +1,104 @@
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
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* Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
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* Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#define TCG_TARGET_MIPS 1
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#define TCG_TARGET_REG_BITS 32
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#ifdef __MIPSEB__
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# define TCG_TARGET_WORDS_BIGENDIAN
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#endif
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#define TCG_TARGET_NB_REGS 32
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enum {
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TCG_REG_ZERO = 0,
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TCG_REG_AT,
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TCG_REG_V0,
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TCG_REG_V1,
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TCG_REG_A0,
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TCG_REG_A1,
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TCG_REG_A2,
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TCG_REG_A3,
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TCG_REG_T0,
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TCG_REG_T1,
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TCG_REG_T2,
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TCG_REG_T3,
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TCG_REG_T4,
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TCG_REG_T5,
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TCG_REG_T6,
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TCG_REG_T7,
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TCG_REG_S0,
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TCG_REG_S1,
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TCG_REG_S2,
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TCG_REG_S3,
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TCG_REG_S4,
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TCG_REG_S5,
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TCG_REG_S6,
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TCG_REG_S7,
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TCG_REG_T8,
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TCG_REG_T9,
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TCG_REG_K0,
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TCG_REG_K1,
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TCG_REG_GP,
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TCG_REG_SP,
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TCG_REG_FP,
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TCG_REG_RA,
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};
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#define TCG_CT_CONST_ZERO 0x100
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#define TCG_CT_CONST_U16 0x200
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#define TCG_CT_CONST_S16 0x400
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/* used for function call generation */
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#define TCG_REG_CALL_STACK TCG_REG_SP
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#define TCG_TARGET_STACK_ALIGN 8
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#define TCG_TARGET_CALL_STACK_OFFSET 16
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#define TCG_TARGET_CALL_ALIGN_ARGS 1
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/* optional instructions */
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#define TCG_TARGET_HAS_div_i32
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#define TCG_TARGET_HAS_not_i32
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#undef TCG_TARGET_HAS_ext8s_i32
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#undef TCG_TARGET_HAS_ext16s_i32
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#undef TCG_TARGET_HAS_bswap32_i32
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#undef TCG_TARGET_HAS_bswap16_i32
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#undef TCG_TARGET_HAS_rot_i32
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/* optional instructions automatically implemented */
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#undef TCG_TARGET_HAS_neg_i32 /* sub rd, zero, rt */
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#undef TCG_TARGET_HAS_ext8u_i32 /* andi rt, rs, 0xff */
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#undef TCG_TARGET_HAS_ext16u_i32 /* andi rt, rs, 0xffff */
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/* Note: must be synced with dyngen-exec.h */
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#define TCG_AREG0 TCG_REG_FP
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#define TCG_AREG1 TCG_REG_S0
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#define TCG_AREG2 TCG_REG_S1
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#include <sys/cachectl.h>
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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cacheflush ((void *)start, stop-start, ICACHE);
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}
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