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onenand: Pass BlockDriverState to init function

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Pass the BlockDriverState to the onenand init function so it doesn't
need to look up the drive itself.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
This commit is contained in:
Peter Maydell 2011-07-29 16:35:25 +01:00 committed by Andrzej Zaborowski
parent d4220389ff
commit af5a75f41c
3 changed files with 12 additions and 10 deletions
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3
hw/flash.h
View file

@ -38,7 +38,8 @@ uint32_t nand_getbuswidth(DeviceState *dev);
/* onenand.c */
void onenand_base_update(void *opaque, target_phys_addr_t new);
void onenand_base_unmap(void *opaque);
void *onenand_init(uint32_t id, int regshift, qemu_irq irq);
void *onenand_init(BlockDriverState *bdrv, uint32_t id,
int regshift, qemu_irq irq);
void *onenand_raw_otp(void *opaque);
/* ecc.c */

10
hw/nseries.c
View file

@ -31,6 +31,7 @@
#include "hw.h"
#include "bt.h"
#include "loader.h"
#include "blockdev.h"
/* Nokia N8x0 support */
struct n800_s {
@ -163,13 +164,14 @@ static const uint8_t n8x0_cal_bt_id[] = {
static void n8x0_nand_setup(struct n800_s *s)
{
char *otp_region;
DriveInfo *dinfo;
dinfo = drive_get(IF_MTD, 0, 0);
/* Either ec40xx or ec48xx are OK for the ID */
s->nand = onenand_init(dinfo ? dinfo->bdrv : 0, 0xec4800, 1,
qdev_get_gpio_in(s->cpu->gpio, N8X0_ONENAND_GPIO));
omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS, 0, onenand_base_update,
onenand_base_unmap,
(s->nand = onenand_init(0xec4800, 1,
qdev_get_gpio_in(s->cpu->gpio,
N8X0_ONENAND_GPIO))));
onenand_base_unmap, s->nand);
otp_region = onenand_raw_otp(s->nand);
memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));

9
hw/onenand.c
View file

@ -615,10 +615,10 @@ static CPUWriteMemoryFunc * const onenand_writefn[] = {
onenand_write,
};
void *onenand_init(uint32_t id, int regshift, qemu_irq irq)
void *onenand_init(BlockDriverState *bdrv, uint32_t id,
int regshift, qemu_irq irq)
{
OneNANDState *s = (OneNANDState *) qemu_mallocz(sizeof(*s));
DriveInfo *dinfo = drive_get(IF_MTD, 0, 0);
uint32_t size = 1 << (24 + ((id >> 12) & 7));
void *ram;
@ -632,11 +632,10 @@ void *onenand_init(uint32_t id, int regshift, qemu_irq irq)
s->density_mask = (id & (1 << 11)) ? (1 << (6 + ((id >> 12) & 7))) : 0;
s->iomemtype = cpu_register_io_memory(onenand_readfn,
onenand_writefn, s, DEVICE_NATIVE_ENDIAN);
if (!dinfo)
s->bdrv = bdrv;
if (!s->bdrv) {
s->image = memset(qemu_malloc(size + (size >> 5)),
0xff, size + (size >> 5));
else
s->bdrv = dinfo->bdrv;
s->otp = memset(qemu_malloc((64 + 2) << PAGE_SHIFT),
0xff, (64 + 2) << PAGE_SHIFT);
s->ram = qemu_ram_alloc(NULL, "onenand.ram", 0xc000 << s->shift);