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https://gitlab.com/qemu-project/qemu
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omap_uart: convert to memory API
Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
parent
f81138ce97
commit
aee39503df
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@ -33,6 +33,7 @@
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#include "loader.h"
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#include "blockdev.h"
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#include "sysbus.h"
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#include "exec-memory.h"
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/* Nokia N8x0 support */
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struct n800_s {
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@ -1275,11 +1276,12 @@ static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
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const char *kernel_cmdline, const char *initrd_filename,
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const char *cpu_model, struct arm_boot_info *binfo, int model)
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{
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MemoryRegion *sysmem = get_system_memory();
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struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
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int sdram_size = binfo->ram_size;
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DisplayState *ds;
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s->cpu = omap2420_mpu_init(sdram_size, cpu_model);
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s->cpu = omap2420_mpu_init(sysmem, sdram_size, cpu_model);
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/* Setup peripherals
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*
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@ -658,7 +658,8 @@ struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
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qemu_irq irq, omap_clk fclk, omap_clk iclk,
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qemu_irq txdma, qemu_irq rxdma,
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const char *label, CharDriverState *chr);
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struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
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struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
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struct omap_target_agent_s *ta,
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qemu_irq irq, omap_clk fclk, omap_clk iclk,
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qemu_irq txdma, qemu_irq rxdma,
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const char *label, CharDriverState *chr);
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@ -952,7 +953,8 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
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const char *core);
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/* omap2.c */
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struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
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struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
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unsigned long sdram_size,
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const char *core);
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# if TARGET_PHYS_ADDR_BITS == 32
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@ -2223,7 +2223,8 @@ static const struct dma_irq_map omap2_dma_irq_map[] = {
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{ 0, OMAP_INT_24XX_SDMA_IRQ3 },
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};
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struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
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struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
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unsigned long sdram_size,
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const char *core)
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{
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struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
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@ -2295,7 +2296,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
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soc_dma_port_add_mem(s->dma, qemu_get_ram_ptr(sram_base),
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OMAP2_SRAM_BASE, s->sram_size);
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s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19),
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s->uart[0] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 19),
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qdev_get_gpio_in(s->ih[0],
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OMAP_INT_24XX_UART1_IRQ),
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omap_findclk(s, "uart1_fclk"),
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@ -2304,7 +2305,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
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s->drq[OMAP24XX_DMA_UART1_RX],
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"uart1",
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serial_hds[0]);
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s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20),
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s->uart[1] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 20),
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qdev_get_gpio_in(s->ih[0],
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OMAP_INT_24XX_UART2_IRQ),
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omap_findclk(s, "uart2_fclk"),
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@ -2313,7 +2314,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
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s->drq[OMAP24XX_DMA_UART2_RX],
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"uart2",
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serial_hds[0] ? serial_hds[1] : NULL);
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s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21),
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s->uart[2] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 21),
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qdev_get_gpio_in(s->ih[0],
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OMAP_INT_24XX_UART3_IRQ),
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omap_findclk(s, "uart3_fclk"),
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@ -26,6 +26,7 @@
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/* UARTs */
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struct omap_uart_s {
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MemoryRegion iomem;
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target_phys_addr_t base;
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SerialState *serial; /* TODO */
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struct omap_target_agent_s *ta;
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@ -68,11 +69,15 @@ struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
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return s;
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}
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static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr)
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static uint64_t omap_uart_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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struct omap_uart_s *s = (struct omap_uart_s *) opaque;
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addr &= 0xff;
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if (size == 4) {
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return omap_badwidth_read8(opaque, addr);
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}
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switch (addr) {
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case 0x20: /* MDR1 */
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return s->mdr[0];
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@ -103,11 +108,14 @@ static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr)
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}
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static void omap_uart_write(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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uint64_t value, unsigned size)
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{
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struct omap_uart_s *s = (struct omap_uart_s *) opaque;
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addr &= 0xff;
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if (size == 4) {
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return omap_badwidth_write8(opaque, addr, value);
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}
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switch (addr) {
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case 0x20: /* MDR1 */
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s->mdr[0] = value & 0x7f;
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@ -145,32 +153,27 @@ static void omap_uart_write(void *opaque, target_phys_addr_t addr,
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}
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}
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static CPUReadMemoryFunc * const omap_uart_readfn[] = {
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omap_uart_read,
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omap_uart_read,
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omap_badwidth_read8,
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static const MemoryRegionOps omap_uart_ops = {
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.read = omap_uart_read,
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.write = omap_uart_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static CPUWriteMemoryFunc * const omap_uart_writefn[] = {
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omap_uart_write,
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omap_uart_write,
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omap_badwidth_write8,
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};
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struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
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struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
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struct omap_target_agent_s *ta,
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qemu_irq irq, omap_clk fclk, omap_clk iclk,
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qemu_irq txdma, qemu_irq rxdma,
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const char *label, CharDriverState *chr)
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{
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target_phys_addr_t base = omap_l4_attach(ta, 0, 0);
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target_phys_addr_t base = omap_l4_attach_region(ta, 0, NULL);
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struct omap_uart_s *s = omap_uart_init(base, irq,
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fclk, iclk, txdma, rxdma, label, chr);
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int iomemtype = cpu_register_io_memory(omap_uart_readfn,
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omap_uart_writefn, s, DEVICE_NATIVE_ENDIAN);
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memory_region_init_io(&s->iomem, &omap_uart_ops, s, "omap.uart", 0x100);
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s->ta = ta;
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cpu_register_physical_memory(base + 0x20, 0x100, iomemtype);
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memory_region_add_subregion(sysmem, base + 0x20, &s->iomem);
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return s;
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}
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