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https://gitlab.com/qemu-project/qemu
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Cirrus fixes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@898 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
1f04275ec1
commit
aeb3c85f59
1 changed files with 50 additions and 37 deletions
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@ -1,8 +1,8 @@
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/*
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* QEMU Cirrus VGA Emulator.
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* QEMU Cirrus CLGD 54xx VGA Emulator.
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*
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* Copyright (c) 2004 Fabrice Bellard
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* Copyright (c) 2004 Suzu
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* Copyright (c) 2004 Makoto Suzuki (suzu)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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@ -22,6 +22,10 @@
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* Reference: Finn Thogersons' VGADOC4b
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* available at http://home.worldonline.dk/~finth/
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*/
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#include "vl.h"
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#include "vga_int.h"
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@ -478,8 +482,8 @@ cirrus_colorexpand_8(CirrusVGAState * s, uint8_t * dst,
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unsigned bitmask;
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int srcskipleft = 0;
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colors[0] = s->gr[0x00];
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colors[1] = s->gr[0x01];
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colors[0] = s->cirrus_shadow_gr0;
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colors[1] = s->cirrus_shadow_gr1;
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bitmask = 0x80 >> srcskipleft;
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bits = *src++;
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@ -504,9 +508,9 @@ cirrus_colorexpand_16(CirrusVGAState * s, uint8_t * dst,
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unsigned index;
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int srcskipleft = 0;
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colors[0][0] = s->gr[0x00];
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colors[0][0] = s->cirrus_shadow_gr0;
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colors[0][1] = s->gr[0x10];
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colors[1][0] = s->gr[0x01];
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colors[1][0] = s->cirrus_shadow_gr1;
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colors[1][1] = s->gr[0x11];
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bitmask = 0x80 >> srcskipleft;
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@ -534,10 +538,10 @@ cirrus_colorexpand_24(CirrusVGAState * s, uint8_t * dst,
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unsigned index;
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int srcskipleft = 0;
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colors[0][0] = s->gr[0x00];
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colors[0][0] = s->cirrus_shadow_gr0;
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colors[0][1] = s->gr[0x10];
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colors[0][2] = s->gr[0x12];
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colors[1][0] = s->gr[0x01];
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colors[1][0] = s->cirrus_shadow_gr1;
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colors[1][1] = s->gr[0x11];
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colors[1][2] = s->gr[0x13];
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@ -567,11 +571,11 @@ cirrus_colorexpand_32(CirrusVGAState * s, uint8_t * dst,
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unsigned index;
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int srcskipleft = 0;
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colors[0][0] = s->gr[0x00];
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colors[0][0] = s->cirrus_shadow_gr0;
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colors[0][1] = s->gr[0x10];
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colors[0][2] = s->gr[0x12];
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colors[0][3] = s->gr[0x14];
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colors[1][0] = s->gr[0x01];
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colors[1][0] = s->cirrus_shadow_gr1;
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colors[1][1] = s->gr[0x11];
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colors[1][2] = s->gr[0x13];
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colors[1][3] = s->gr[0x15];
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@ -1103,7 +1107,7 @@ static int cirrus_get_bpp(VGAState *s1)
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}
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} else {
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/* VGA */
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ret = 8;
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ret = 0;
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}
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return ret;
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@ -1172,6 +1176,25 @@ cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
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case 0x06: // Unlock Cirrus extensions
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*reg_value = s->sr[reg_index];
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break;
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case 0x10:
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case 0x30:
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case 0x50:
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case 0x70: // Graphics Cursor X
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case 0x90:
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case 0xb0:
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case 0xd0:
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case 0xf0: // Graphics Cursor X
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*reg_value = s->sr[0x10];
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break;
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case 0x11:
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case 0x31:
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case 0x51:
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case 0x71: // Graphics Cursor Y
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case 0x91:
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case 0xb1:
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case 0xd1:
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*reg_value = s->sr[0x11];
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break;
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case 0x05: // ???
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case 0x07: // Extended Sequencer Mode
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case 0x08: // EEPROM Control
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@ -1182,21 +1205,6 @@ cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
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case 0x0d: // VCLK 2
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case 0x0e: // VCLK 3
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case 0x0f: // DRAM Control
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case 0x10:
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case 0x30:
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case 0x50:
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case 0x70: // Graphics Cursor X
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case 0x90:
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case 0xb0:
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case 0xd0:
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case 0xf0: // Graphics Cursor X
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case 0x11:
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case 0x31:
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case 0x51:
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case 0x71: // Graphics Cursor Y
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case 0x91:
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case 0xb1:
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case 0xd1:
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case 0xf1: // Graphics Cursor Y
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case 0x12: // Graphics Cursor Attribute
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case 0x13: // Graphics Cursor Pattern Address
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@ -1387,6 +1395,12 @@ static int
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cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
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{
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switch (reg_index) {
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case 0x00: // Standard VGA, BGCOLOR 0x000000ff
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*reg_value = s->cirrus_shadow_gr0;
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return CIRRUS_HOOK_HANDLED;
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case 0x01: // Standard VGA, FGCOLOR 0x000000ff
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*reg_value = s->cirrus_shadow_gr1;
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return CIRRUS_HOOK_HANDLED;
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case 0x02: // Standard VGA
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case 0x03: // Standard VGA
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case 0x04: // Standard VGA
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@ -1416,10 +1430,10 @@ cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
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{
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switch (reg_index) {
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case 0x00: // Standard VGA, BGCOLOR 0x000000ff
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s->gr[0x00] = reg_value;
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s->cirrus_shadow_gr0 = reg_value;
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return CIRRUS_HOOK_NOT_HANDLED;
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case 0x01: // Standard VGA, FGCOLOR 0x000000ff
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s->gr[0x01] = reg_value;
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s->cirrus_shadow_gr1 = reg_value;
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return CIRRUS_HOOK_NOT_HANDLED;
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case 0x02: // Standard VGA
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case 0x03: // Standard VGA
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@ -1840,9 +1854,9 @@ static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
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dst = s->vram_ptr + offset;
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for (x = 0; x < 8; x++) {
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if (val & 0x80) {
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*dst++ = s->gr[0x01];
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*dst++ = s->cirrus_shadow_gr1;
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} else if (mode == 5) {
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*dst++ = s->gr[0x00];
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*dst++ = s->cirrus_shadow_gr0;
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}
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val <<= 1;
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}
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@ -1862,10 +1876,10 @@ static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
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dst = s->vram_ptr + offset;
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for (x = 0; x < 8; x++) {
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if (val & 0x80) {
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*dst++ = s->gr[0x01];
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*dst++ = s->cirrus_shadow_gr1;
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*dst++ = s->gr[0x11];
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} else if (mode == 5) {
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*dst++ = s->gr[0x00];
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*dst++ = s->cirrus_shadow_gr0;
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*dst++ = s->gr[0x10];
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}
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val <<= 1;
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@ -1891,6 +1905,8 @@ static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
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return vga_mem_readb(s, addr);
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}
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addr &= 0x1ffff;
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if (addr < 0x10000) {
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/* XXX handle bitblt */
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/* video memory */
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@ -1965,6 +1981,8 @@ static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
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return;
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}
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addr &= 0x1ffff;
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if (addr < 0x10000) {
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if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
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/* bitblt */
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@ -2282,11 +2300,6 @@ static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
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val = s->cr[s->cr_index];
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#ifdef DEBUG_VGA_REG
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printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
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#endif
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#ifdef DEBUG_S3
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if (s->cr_index >= 0x20)
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printf("S3: CR read index=0x%x val=0x%x\n",
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s->cr_index, val);
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#endif
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break;
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case 0x3ba:
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