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ppc/pnv: add a PSI bridge class model
To ease the introduction of the PSI bridge model for POWER9, abstract the POWER chip differences in a PnvPsi class model and introduce a specific Pnv8Psi type for POWER8. POWER8 interface to the interrupt controller is still XICS whereas POWER9 uses the new XIVE model. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190307223548.20516-2-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater
David Gibson
parent
31bc6fa7fa
commit
ae85605531
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@ -788,7 +788,7 @@ static void pnv_chip_power8_instance_init(Object *obj)
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Pnv8Chip *chip8 = PNV8_CHIP(obj);
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object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi),
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TYPE_PNV_PSI, &error_abort, NULL);
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TYPE_PNV8_PSI, &error_abort, NULL);
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object_property_add_const_link(OBJECT(&chip8->psi), "xics",
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OBJECT(qdev_get_machine()), &error_abort);
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@ -840,6 +840,7 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
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PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
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PnvChip *chip = PNV_CHIP(dev);
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Pnv8Chip *chip8 = PNV8_CHIP(dev);
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Pnv8Psi *psi8 = &chip8->psi;
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Error *local_err = NULL;
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pcc->parent_realize(dev, &local_err);
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@ -856,7 +857,8 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
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error_propagate(errp, local_err);
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return;
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}
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pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip8->psi.xscom_regs);
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pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
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&PNV_PSI(psi8)->xscom_regs);
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/* Create LPC controller */
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object_property_set_bool(OBJECT(&chip8->lpc), true, "realized",
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@ -118,10 +118,11 @@
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static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar)
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{
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PnvPsiClass *ppc = PNV_PSI_GET_CLASS(psi);
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MemoryRegion *sysmem = get_system_memory();
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uint64_t old = psi->regs[PSIHB_XSCOM_BAR];
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psi->regs[PSIHB_XSCOM_BAR] = bar & (PSIHB_BAR_MASK | PSIHB_BAR_EN);
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psi->regs[PSIHB_XSCOM_BAR] = bar & (ppc->bar_mask | PSIHB_BAR_EN);
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/* Update MR, always remove it first */
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if (old & PSIHB_BAR_EN) {
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@ -130,7 +131,7 @@ static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar)
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/* Then add it back if needed */
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if (bar & PSIHB_BAR_EN) {
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uint64_t addr = bar & PSIHB_BAR_MASK;
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uint64_t addr = bar & ppc->bar_mask;
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memory_region_add_subregion(sysmem, addr, &psi->regs_mr);
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}
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}
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@ -154,7 +155,7 @@ static void pnv_psi_set_cr(PnvPsi *psi, uint64_t cr)
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static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val)
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{
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ICSState *ics = &psi->ics;
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ICSState *ics = &PNV8_PSI(psi)->ics;
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/* In this model we ignore the up/down enable bits for now
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* as SW doesn't use them (other than setting them at boot).
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@ -207,7 +208,12 @@ static const uint64_t stat_bits[] = {
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[PSIHB_IRQ_EXTERNAL] = PSIHB_IRQ_STAT_EXT,
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};
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void pnv_psi_irq_set(PnvPsi *psi, PnvPsiIrq irq, bool state)
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void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state)
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{
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PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state);
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}
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static void pnv_psi_power8_irq_set(PnvPsi *psi, int irq, bool state)
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{
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uint32_t xivr_reg;
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uint32_t stat_reg;
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@ -262,7 +268,7 @@ void pnv_psi_irq_set(PnvPsi *psi, PnvPsiIrq irq, bool state)
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static void pnv_psi_set_xivr(PnvPsi *psi, uint32_t reg, uint64_t val)
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{
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ICSState *ics = &psi->ics;
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ICSState *ics = &PNV8_PSI(psi)->ics;
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uint16_t server;
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uint8_t prio;
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uint8_t src;
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@ -451,11 +457,11 @@ static void pnv_psi_reset(void *dev)
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psi->regs[PSIHB_XSCOM_BAR] = psi->bar | PSIHB_BAR_EN;
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}
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static void pnv_psi_init(Object *obj)
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static void pnv_psi_power8_instance_init(Object *obj)
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{
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PnvPsi *psi = PNV_PSI(obj);
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Pnv8Psi *psi8 = PNV8_PSI(obj);
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object_initialize_child(obj, "ics-psi", &psi->ics, sizeof(psi->ics),
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object_initialize_child(obj, "ics-psi", &psi8->ics, sizeof(psi8->ics),
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TYPE_ICS_SIMPLE, &error_abort, NULL);
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}
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@ -468,10 +474,10 @@ static const uint8_t irq_to_xivr[] = {
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PSIHB_XSCOM_XIVR_EXT,
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};
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static void pnv_psi_realize(DeviceState *dev, Error **errp)
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static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
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{
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PnvPsi *psi = PNV_PSI(dev);
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ICSState *ics = &psi->ics;
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ICSState *ics = &PNV8_PSI(psi)->ics;
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Object *obj;
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Error *err = NULL;
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unsigned int i;
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@ -524,28 +530,28 @@ static void pnv_psi_realize(DeviceState *dev, Error **errp)
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qemu_register_reset(pnv_psi_reset, dev);
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}
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static const char compat_p8[] = "ibm,power8-psihb-x\0ibm,psihb-x";
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static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
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{
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const char compat[] = "ibm,power8-psihb-x\0ibm,psihb-x";
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PnvPsiClass *ppc = PNV_PSI_GET_CLASS(dev);
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char *name;
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int offset;
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uint32_t lpc_pcba = PNV_XSCOM_PSIHB_BASE;
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uint32_t reg[] = {
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cpu_to_be32(lpc_pcba),
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cpu_to_be32(PNV_XSCOM_PSIHB_SIZE)
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cpu_to_be32(ppc->xscom_pcba),
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cpu_to_be32(ppc->xscom_size)
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};
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name = g_strdup_printf("psihb@%x", lpc_pcba);
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name = g_strdup_printf("psihb@%x", ppc->xscom_pcba);
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offset = fdt_add_subnode(fdt, xscom_offset, name);
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_FDT(offset);
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g_free(name);
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_FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
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_FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2)));
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_FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1)));
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_FDT((fdt_setprop(fdt, offset, "compatible", compat,
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sizeof(compat))));
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_FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)));
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_FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2));
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_FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1));
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_FDT(fdt_setprop(fdt, offset, "compatible", compat_p8,
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sizeof(compat_p8)));
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return 0;
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}
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@ -555,6 +561,29 @@ static Property pnv_psi_properties[] = {
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DEFINE_PROP_END_OF_LIST(),
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};
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static void pnv_psi_power8_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
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dc->desc = "PowerNV PSI Controller POWER8";
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dc->realize = pnv_psi_power8_realize;
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ppc->chip_type = PNV_CHIP_POWER8;
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ppc->xscom_pcba = PNV_XSCOM_PSIHB_BASE;
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ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE;
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ppc->bar_mask = PSIHB_BAR_MASK;
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ppc->irq_set = pnv_psi_power8_irq_set;
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}
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static const TypeInfo pnv_psi_power8_info = {
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.name = TYPE_PNV8_PSI,
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.parent = TYPE_PNV_PSI,
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.instance_size = sizeof(Pnv8Psi),
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.instance_init = pnv_psi_power8_instance_init,
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.class_init = pnv_psi_power8_class_init,
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};
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static void pnv_psi_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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@ -562,7 +591,7 @@ static void pnv_psi_class_init(ObjectClass *klass, void *data)
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xdc->dt_xscom = pnv_psi_dt_xscom;
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dc->realize = pnv_psi_realize;
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dc->desc = "PowerNV PSI Controller";
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dc->props = pnv_psi_properties;
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}
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@ -570,8 +599,9 @@ static const TypeInfo pnv_psi_info = {
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.name = TYPE_PNV_PSI,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(PnvPsi),
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.instance_init = pnv_psi_init,
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.class_init = pnv_psi_class_init,
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.class_size = sizeof(PnvPsiClass),
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.abstract = true,
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.interfaces = (InterfaceInfo[]) {
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{ TYPE_PNV_XSCOM_INTERFACE },
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{ }
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@ -581,6 +611,7 @@ static const TypeInfo pnv_psi_info = {
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static void pnv_psi_register_types(void)
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{
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type_register_static(&pnv_psi_info);
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type_register_static(&pnv_psi_power8_info);
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}
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type_init(pnv_psi_register_types)
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type_init(pnv_psi_register_types);
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@ -71,7 +71,7 @@ typedef struct Pnv8Chip {
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MemoryRegion icp_mmio;
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PnvLpcController lpc;
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PnvPsi psi;
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Pnv8Psi psi;
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PnvOCC occ;
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} Pnv8Chip;
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@ -39,7 +39,6 @@ typedef struct PnvPsi {
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uint64_t fsp_bar;
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/* Interrupt generation */
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ICSState ics;
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qemu_irq *qirqs;
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/* Registers */
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@ -48,6 +47,32 @@ typedef struct PnvPsi {
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MemoryRegion xscom_regs;
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} PnvPsi;
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#define TYPE_PNV8_PSI TYPE_PNV_PSI "-POWER8"
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#define PNV8_PSI(obj) \
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OBJECT_CHECK(Pnv8Psi, (obj), TYPE_PNV8_PSI)
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typedef struct Pnv8Psi {
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PnvPsi parent;
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ICSState ics;
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} Pnv8Psi;
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#define PNV_PSI_CLASS(klass) \
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OBJECT_CLASS_CHECK(PnvPsiClass, (klass), TYPE_PNV_PSI)
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#define PNV_PSI_GET_CLASS(obj) \
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OBJECT_GET_CLASS(PnvPsiClass, (obj), TYPE_PNV_PSI)
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typedef struct PnvPsiClass {
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SysBusDeviceClass parent_class;
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int chip_type;
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uint32_t xscom_pcba;
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uint32_t xscom_size;
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uint64_t bar_mask;
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void (*irq_set)(PnvPsi *psi, int, bool state);
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} PnvPsiClass;
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/* The PSI and FSP interrupts are muxed on the same IRQ number */
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typedef enum PnvPsiIrq {
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PSIHB_IRQ_PSI, /* internal use only */
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@ -61,6 +86,6 @@ typedef enum PnvPsiIrq {
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#define PSI_NUM_INTERRUPTS 6
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extern void pnv_psi_irq_set(PnvPsi *psi, PnvPsiIrq irq, bool state);
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void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state);
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#endif /* _PPC_PNV_PSI_H */
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