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tcg: Add load_dest parameter to GVecGen2
We have this same parameter for GVecGen2i, GVecGen3, and GVecGen3i. This will make some SVE2 insns easier to parameterize. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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f47db80cc0
commit
ac09ae627e
2 changed files with 34 additions and 13 deletions
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@ -109,6 +109,8 @@ typedef struct {
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uint8_t vece;
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/* Prefer i64 to v64. */
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bool prefer_i64;
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/* Load dest as a 2nd source operand. */
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bool load_dest;
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} GVecGen2;
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typedef struct {
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@ -663,17 +663,22 @@ static void expand_clr(uint32_t dofs, uint32_t maxsz)
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/* Expand OPSZ bytes worth of two-operand operations using i32 elements. */
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static void expand_2_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
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void (*fni)(TCGv_i32, TCGv_i32))
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bool load_dest, void (*fni)(TCGv_i32, TCGv_i32))
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{
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TCGv_i32 t0 = tcg_temp_new_i32();
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TCGv_i32 t1 = tcg_temp_new_i32();
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uint32_t i;
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for (i = 0; i < oprsz; i += 4) {
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tcg_gen_ld_i32(t0, cpu_env, aofs + i);
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fni(t0, t0);
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tcg_gen_st_i32(t0, cpu_env, dofs + i);
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if (load_dest) {
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tcg_gen_ld_i32(t1, cpu_env, dofs + i);
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}
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fni(t1, t0);
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tcg_gen_st_i32(t1, cpu_env, dofs + i);
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}
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tcg_temp_free_i32(t0);
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tcg_temp_free_i32(t1);
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}
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static void expand_2i_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
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@ -793,17 +798,22 @@ static void expand_4_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
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/* Expand OPSZ bytes worth of two-operand operations using i64 elements. */
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static void expand_2_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
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void (*fni)(TCGv_i64, TCGv_i64))
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bool load_dest, void (*fni)(TCGv_i64, TCGv_i64))
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{
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TCGv_i64 t0 = tcg_temp_new_i64();
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TCGv_i64 t1 = tcg_temp_new_i64();
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uint32_t i;
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for (i = 0; i < oprsz; i += 8) {
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tcg_gen_ld_i64(t0, cpu_env, aofs + i);
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fni(t0, t0);
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tcg_gen_st_i64(t0, cpu_env, dofs + i);
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if (load_dest) {
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tcg_gen_ld_i64(t1, cpu_env, dofs + i);
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}
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fni(t1, t0);
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tcg_gen_st_i64(t1, cpu_env, dofs + i);
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}
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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}
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static void expand_2i_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
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@ -924,17 +934,23 @@ static void expand_4_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
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/* Expand OPSZ bytes worth of two-operand operations using host vectors. */
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static void expand_2_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
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uint32_t oprsz, uint32_t tysz, TCGType type,
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bool load_dest,
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void (*fni)(unsigned, TCGv_vec, TCGv_vec))
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{
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TCGv_vec t0 = tcg_temp_new_vec(type);
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TCGv_vec t1 = tcg_temp_new_vec(type);
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uint32_t i;
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for (i = 0; i < oprsz; i += tysz) {
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tcg_gen_ld_vec(t0, cpu_env, aofs + i);
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fni(vece, t0, t0);
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tcg_gen_st_vec(t0, cpu_env, dofs + i);
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if (load_dest) {
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tcg_gen_ld_vec(t1, cpu_env, dofs + i);
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}
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fni(vece, t1, t0);
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tcg_gen_st_vec(t1, cpu_env, dofs + i);
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}
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tcg_temp_free_vec(t0);
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tcg_temp_free_vec(t1);
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}
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/* Expand OPSZ bytes worth of two-vector operands and an immediate operand
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@ -1088,7 +1104,8 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
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* that e.g. size == 80 would be expanded with 2x32 + 1x16.
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*/
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some = QEMU_ALIGN_DOWN(oprsz, 32);
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expand_2_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256, g->fniv);
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expand_2_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256,
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g->load_dest, g->fniv);
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if (some == oprsz) {
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break;
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}
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@ -1098,17 +1115,19 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
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maxsz -= some;
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/* fallthru */
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case TCG_TYPE_V128:
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expand_2_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, g->fniv);
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expand_2_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128,
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g->load_dest, g->fniv);
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break;
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case TCG_TYPE_V64:
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expand_2_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, g->fniv);
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expand_2_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64,
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g->load_dest, g->fniv);
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break;
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case 0:
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if (g->fni8 && check_size_impl(oprsz, 8)) {
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expand_2_i64(dofs, aofs, oprsz, g->fni8);
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expand_2_i64(dofs, aofs, oprsz, g->load_dest, g->fni8);
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} else if (g->fni4 && check_size_impl(oprsz, 4)) {
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expand_2_i32(dofs, aofs, oprsz, g->fni4);
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expand_2_i32(dofs, aofs, oprsz, g->load_dest, g->fni4);
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} else {
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assert(g->fno != NULL);
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tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, g->data, g->fno);
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