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target-arm queue
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABCAAGBQJR5CARAAoJEDwlJe0UNgze2MYP/RzOLWiGX7Y4byy0XUYKupXW H4H43HVjt98V/PrJl/u3MA4mjI7EjgnO/WmWtqdj+GpCWJ47lCrYjdIH50IeG4Ug /ZR8GuVBvPmQeUDNL0as8c/aHJ4WCnAM8z08FKkjN1YWfamBgOL3CNdSZAxqORw6 xnHnmGbTqX5JfW78k9R6mSP5z1VRoOzXyMLSRso5ySzH+sLlAGCXYITaTGqDxoNu MnJZsa+E6bfOURVI0rodqwS8N2Pe6VBHWXQt7Jrll5fMGxvhbqteRU+pzXpzU9H/ 3oeROVLL3kK6n22AXmGgjszPQ2Dus0NhPqRiMml98SnsF5+4d9e/dVtVYJZkuusT 6uxrOIBu6OEdpl6siBuuZMNSVf4hXMPCVgIxi0pQpRt145VjRGcbzzEBII8ZRK8z tfzzwDW4m0K/UqV2D9RxG/86DEh0pBb0YvXoNFCMlbg1hKpbH/E7kGedRScffApE Pygo6lKcf3b4rpJCvNmGQOz8PS0mfqqUdasgyCeTw0QOgvHnbS6WsnEng/12PpTt 7AFILRngiwds7VUbnN0jtoEYerJmEoU8DTZWsehArcO/duVZE58FoSxMweNnLhDr gZJRMqEEq0ZWbqmDFcJXcvArtgfBiTHySWcLx4KuWL6GL0Oe4efR5ABMmUdCv7+5 ELiTRIKbagL03/sgUPQ1 =PySE -----END PGP SIGNATURE----- Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20130715-1' into staging target-arm queue # gpg: Signature made Mon 15 Jul 2013 11:15:13 AM CDT using RSA key ID 14360CDE # gpg: Can't check signature: public key not found # By Mans Rullgard (3) and others # Via Peter Maydell * pmaydell/tags/pull-target-arm-20130715-1: target-arm: Avoid g_hash_table_get_keys() target-arm: avoid undefined behaviour when writing TTBCR target-arm/helper.c: Allow const opaques in arm CP target-arm/helper.c: Implement MIDR aliases target-arm/helper.c: OMAP/StrongARM cp15 crn=0 cleanup target-arm: explicitly decode SEVL instruction target-arm: implement LDA/STL instructions target-arm: add feature flag for ARMv8 Message-id: 1373905022-27735-1-git-send-email-peter.maydell@linaro.org Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Anthony Liguori
commit
ab4e1589f0
4 changed files with 161 additions and 31 deletions
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@ -157,6 +157,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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CPUARMState *env = &cpu->env;
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/* Some features automatically imply others: */
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if (arm_feature(env, ARM_FEATURE_V8)) {
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set_feature(env, ARM_FEATURE_V7);
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set_feature(env, ARM_FEATURE_ARM_DIV);
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set_feature(env, ARM_FEATURE_LPAE);
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}
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if (arm_feature(env, ARM_FEATURE_V7)) {
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set_feature(env, ARM_FEATURE_VAPA);
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set_feature(env, ARM_FEATURE_THUMB2);
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@ -744,7 +749,7 @@ static void pxa270c5_initfn(Object *obj)
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static void arm_any_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V7);
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_VFP4);
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set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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@ -387,6 +387,7 @@ enum arm_features {
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ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
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ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
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ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
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ARM_FEATURE_V8,
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};
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static inline int arm_feature(CPUARMState *env, int feature)
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@ -222,15 +222,23 @@ static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
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return aidx - bidx;
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}
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static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
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{
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GList **plist = udata;
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*plist = g_list_prepend(*plist, key);
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}
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void init_cpreg_list(ARMCPU *cpu)
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{
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/* Initialise the cpreg_tuples[] array based on the cp_regs hash.
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* Note that we require cpreg_tuples[] to be sorted by key ID.
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*/
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GList *keys;
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GList *keys = NULL;
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int arraylen;
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keys = g_hash_table_get_keys(cpu->cp_regs);
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g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
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keys = g_list_sort(keys, cpreg_key_compare);
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cpu->cpreg_array_len = 0;
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@ -891,6 +899,8 @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
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static int vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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int maskshift = extract32(value, 0, 3);
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if (arm_feature(env, ARM_FEATURE_LPAE)) {
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value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
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} else {
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@ -902,8 +912,8 @@ static int vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
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* and the c2_mask and c2_base_mask values are meaningless.
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*/
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env->cp15.c2_control = value;
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env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> value);
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env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> value);
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env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
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env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
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return 0;
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}
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@ -1378,9 +1388,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
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define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
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}
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if (arm_feature(env, ARM_FEATURE_MPIDR)) {
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define_arm_cp_regs(cpu, mpidr_cp_reginfo);
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}
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if (arm_feature(env, ARM_FEATURE_LPAE)) {
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define_arm_cp_regs(cpu, lpae_cp_reginfo);
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}
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@ -1393,12 +1400,17 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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/* Note that the MIDR isn't a simple constant register because
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* of the TI925 behaviour where writes to another register can
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* cause the MIDR value to change.
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*
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* Unimplemented registers in the c15 0 0 0 space default to
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* MIDR. Define MIDR first as this entire space, then CTR, TCMTR
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* and friends override accordingly.
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*/
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{ .name = "MIDR",
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.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
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.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
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.access = PL1_R, .resetvalue = cpu->midr,
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.writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
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.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid) },
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.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
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.type = ARM_CP_OVERRIDE },
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{ .name = "CTR",
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.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
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.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
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@ -1435,21 +1447,20 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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arm_feature(env, ARM_FEATURE_STRONGARM)) {
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ARMCPRegInfo *r;
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/* Register the blanket "writes ignored" value first to cover the
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* whole space. Then define the specific ID registers, but update
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* their access field to allow write access, so that they ignore
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* writes rather than causing them to UNDEF.
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* whole space. Then update the specific ID registers to allow write
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* access, so that they ignore writes rather than causing them to
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* UNDEF.
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*/
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define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
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for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
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r->access = PL1_RW;
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define_one_arm_cp_reg(cpu, r);
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}
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} else {
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/* Just register the standard ID registers (read-only, meaning
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* that writes will UNDEF).
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*/
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define_arm_cp_regs(cpu, id_cp_reginfo);
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}
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define_arm_cp_regs(cpu, id_cp_reginfo);
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}
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if (arm_feature(env, ARM_FEATURE_MPIDR)) {
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define_arm_cp_regs(cpu, mpidr_cp_reginfo);
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}
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if (arm_feature(env, ARM_FEATURE_AUXCR)) {
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@ -1607,7 +1618,9 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
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ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
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int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
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*key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2);
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r2->opaque = opaque;
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if (opaque) {
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r2->opaque = opaque;
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}
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/* Make sure reginfo passed to helpers for wildcarded regs
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* has the correct crm/opc1/opc2 for this reg, not CP_ANY:
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*/
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@ -42,6 +42,7 @@
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#define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
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#define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
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#define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
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#define ENABLE_ARCH_8 arm_feature(env, ARM_FEATURE_V8)
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#define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
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@ -3500,7 +3501,8 @@ static void gen_nop_hint(DisasContext *s, int val)
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break;
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case 2: /* wfe */
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case 4: /* sev */
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/* TODO: Implement SEV and WFE. May help SMP performance. */
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case 5: /* sevl */
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/* TODO: Implement SEV, SEVL and WFE. May help SMP performance. */
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default: /* nop */
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break;
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}
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@ -7273,14 +7275,72 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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rd = (insn >> 12) & 0xf;
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if (insn & (1 << 23)) {
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/* load/store exclusive */
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int op2 = (insn >> 8) & 3;
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op1 = (insn >> 21) & 0x3;
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if (op1)
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ARCH(6K);
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else
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ARCH(6);
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switch (op2) {
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case 0: /* lda/stl */
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if (op1 == 1) {
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goto illegal_op;
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}
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ARCH(8);
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break;
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case 1: /* reserved */
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goto illegal_op;
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case 2: /* ldaex/stlex */
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ARCH(8);
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break;
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case 3: /* ldrex/strex */
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if (op1) {
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ARCH(6K);
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} else {
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ARCH(6);
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}
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break;
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}
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addr = tcg_temp_local_new_i32();
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load_reg_var(s, addr, rn);
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if (insn & (1 << 20)) {
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/* Since the emulation does not have barriers,
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the acquire/release semantics need no special
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handling */
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if (op2 == 0) {
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if (insn & (1 << 20)) {
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tmp = tcg_temp_new_i32();
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switch (op1) {
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case 0: /* lda */
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tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
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break;
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case 2: /* ldab */
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tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
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break;
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case 3: /* ldah */
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tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
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break;
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default:
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abort();
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}
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store_reg(s, rd, tmp);
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} else {
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rm = insn & 0xf;
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tmp = load_reg(s, rm);
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switch (op1) {
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case 0: /* stl */
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tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
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break;
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case 2: /* stlb */
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tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
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break;
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case 3: /* stlh */
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tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
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break;
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default:
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abort();
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}
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tcg_temp_free_i32(tmp);
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}
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} else if (insn & (1 << 20)) {
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switch (op1) {
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case 0: /* ldrex */
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gen_load_exclusive(s, rd, 15, addr, 2);
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@ -8125,7 +8185,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
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gen_store_exclusive(s, rd, rs, 15, addr, 2);
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}
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tcg_temp_free_i32(addr);
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} else if ((insn & (1 << 6)) == 0) {
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} else if ((insn & (7 << 5)) == 0) {
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/* Table Branch. */
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if (rn == 15) {
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addr = tcg_temp_new_i32();
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@ -8151,15 +8211,66 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
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tcg_gen_addi_i32(tmp, tmp, s->pc);
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store_reg(s, 15, tmp);
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} else {
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/* Load/store exclusive byte/halfword/doubleword. */
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ARCH(7);
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int op2 = (insn >> 6) & 0x3;
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op = (insn >> 4) & 0x3;
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if (op == 2) {
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switch (op2) {
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case 0:
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goto illegal_op;
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case 1:
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/* Load/store exclusive byte/halfword/doubleword */
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if (op == 2) {
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goto illegal_op;
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}
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ARCH(7);
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break;
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case 2:
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/* Load-acquire/store-release */
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if (op == 3) {
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goto illegal_op;
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}
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/* Fall through */
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case 3:
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/* Load-acquire/store-release exclusive */
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ARCH(8);
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break;
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}
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addr = tcg_temp_local_new_i32();
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load_reg_var(s, addr, rn);
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if (insn & (1 << 20)) {
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if (!(op2 & 1)) {
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if (insn & (1 << 20)) {
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tmp = tcg_temp_new_i32();
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switch (op) {
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case 0: /* ldab */
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tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
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break;
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case 1: /* ldah */
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tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
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break;
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case 2: /* lda */
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tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
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break;
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default:
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abort();
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}
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store_reg(s, rs, tmp);
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} else {
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tmp = load_reg(s, rs);
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switch (op) {
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case 0: /* stlb */
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tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
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break;
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case 1: /* stlh */
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tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
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break;
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case 2: /* stl */
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tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
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break;
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default:
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abort();
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}
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tcg_temp_free_i32(tmp);
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}
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} else if (insn & (1 << 20)) {
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gen_load_exclusive(s, rs, rd, addr, op);
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} else {
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gen_store_exclusive(s, rm, rs, rd, addr, op);
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