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i386: Clean up cache CPUID code
Always initialize CPUCaches structs with cache information, even if legacy_cache=true. Use different CPUCaches struct for CPUID[2], CPUID[4], and the AMD CPUID leaves. This will simplify a lot the logic inside cpu_x86_cpuid(). Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Babu Moger <babu.moger@amd.com> Message-Id: <1527176614-26271-2-git-send-email-babu.moger@amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
This commit is contained in:
Eduardo Habkost
parent
0d2fa03dae
commit
a9f27ea9ad
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@ -1112,7 +1112,7 @@ struct X86CPUDefinition {
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};
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static CPUCaches epyc_cache_info = {
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.l1d_cache = {
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.l1d_cache = &(CPUCacheInfo) {
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.type = DCACHE,
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.level = 1,
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.size = 32 * KiB,
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@ -1124,7 +1124,7 @@ static CPUCaches epyc_cache_info = {
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.self_init = 1,
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.no_invd_sharing = true,
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},
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.l1i_cache = {
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.l1i_cache = &(CPUCacheInfo) {
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.type = ICACHE,
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.level = 1,
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.size = 64 * KiB,
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@ -1136,7 +1136,7 @@ static CPUCaches epyc_cache_info = {
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.self_init = 1,
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.no_invd_sharing = true,
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},
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.l2_cache = {
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.l2_cache = &(CPUCacheInfo) {
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.type = UNIFIED_CACHE,
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.level = 2,
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.size = 512 * KiB,
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@ -1146,7 +1146,7 @@ static CPUCaches epyc_cache_info = {
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.sets = 1024,
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.lines_per_tag = 1,
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},
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.l3_cache = {
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.l3_cache = &(CPUCacheInfo) {
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.type = UNIFIED_CACHE,
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.level = 3,
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.size = 8 * MiB,
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@ -3340,9 +3340,8 @@ static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
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env->features[w] = def->features[w];
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}
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/* Store Cache information from the X86CPUDefinition if available */
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env->cache_info = def->cache_info;
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cpu->legacy_cache = def->cache_info ? 0 : 1;
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/* legacy-cache defaults to 'off' if CPU model provides cache info */
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cpu->legacy_cache = !def->cache_info;
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/* Special cases not set in the X86CPUDefinition structs: */
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/* TODO: in-kernel irqchip for hvf */
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@ -3693,21 +3692,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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if (!cpu->enable_l3_cache) {
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*ecx = 0;
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} else {
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if (env->cache_info && !cpu->legacy_cache) {
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*ecx = cpuid2_cache_descriptor(&env->cache_info->l3_cache);
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} else {
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*ecx = cpuid2_cache_descriptor(&legacy_l3_cache);
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}
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}
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if (env->cache_info && !cpu->legacy_cache) {
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*edx = (cpuid2_cache_descriptor(&env->cache_info->l1d_cache) << 16) |
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(cpuid2_cache_descriptor(&env->cache_info->l1i_cache) << 8) |
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(cpuid2_cache_descriptor(&env->cache_info->l2_cache));
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} else {
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*edx = (cpuid2_cache_descriptor(&legacy_l1d_cache) << 16) |
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(cpuid2_cache_descriptor(&legacy_l1i_cache) << 8) |
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(cpuid2_cache_descriptor(&legacy_l2_cache_cpuid2));
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*ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
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}
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*edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
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(cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
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(cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
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break;
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case 4:
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/* cache info: needed for Core compatibility */
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@ -3720,35 +3709,27 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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}
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} else {
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*eax = 0;
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CPUCacheInfo *l1d, *l1i, *l2, *l3;
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if (env->cache_info && !cpu->legacy_cache) {
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l1d = &env->cache_info->l1d_cache;
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l1i = &env->cache_info->l1i_cache;
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l2 = &env->cache_info->l2_cache;
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l3 = &env->cache_info->l3_cache;
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} else {
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l1d = &legacy_l1d_cache;
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l1i = &legacy_l1i_cache;
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l2 = &legacy_l2_cache;
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l3 = &legacy_l3_cache;
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}
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switch (count) {
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case 0: /* L1 dcache info */
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encode_cache_cpuid4(l1d, 1, cs->nr_cores,
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encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
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1, cs->nr_cores,
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eax, ebx, ecx, edx);
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break;
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case 1: /* L1 icache info */
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encode_cache_cpuid4(l1i, 1, cs->nr_cores,
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encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
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1, cs->nr_cores,
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eax, ebx, ecx, edx);
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break;
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case 2: /* L2 cache info */
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encode_cache_cpuid4(l2, cs->nr_threads, cs->nr_cores,
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encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
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cs->nr_threads, cs->nr_cores,
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eax, ebx, ecx, edx);
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break;
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case 3: /* L3 cache info */
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pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
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if (cpu->enable_l3_cache) {
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encode_cache_cpuid4(l3, (1 << pkg_offset), cs->nr_cores,
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encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
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(1 << pkg_offset), cs->nr_cores,
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eax, ebx, ecx, edx);
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break;
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}
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@ -3961,13 +3942,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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(L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
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*ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
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(L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
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if (env->cache_info && !cpu->legacy_cache) {
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*ecx = encode_cache_cpuid80000005(&env->cache_info->l1d_cache);
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*edx = encode_cache_cpuid80000005(&env->cache_info->l1i_cache);
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} else {
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*ecx = encode_cache_cpuid80000005(&legacy_l1d_cache_amd);
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*edx = encode_cache_cpuid80000005(&legacy_l1i_cache_amd);
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}
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*ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
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*edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
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break;
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case 0x80000006:
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/* cache info (L2 cache) */
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@ -3983,17 +3959,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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(L2_DTLB_4K_ENTRIES << 16) | \
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(AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
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(L2_ITLB_4K_ENTRIES);
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if (env->cache_info && !cpu->legacy_cache) {
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encode_cache_cpuid80000006(&env->cache_info->l2_cache,
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cpu->enable_l3_cache ?
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&env->cache_info->l3_cache : NULL,
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ecx, edx);
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} else {
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encode_cache_cpuid80000006(&legacy_l2_cache_amd,
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cpu->enable_l3_cache ?
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&legacy_l3_cache : NULL,
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ecx, edx);
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}
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encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
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cpu->enable_l3_cache ?
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env->cache_info_amd.l3_cache : NULL,
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ecx, edx);
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break;
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case 0x80000007:
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*eax = 0;
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@ -4690,6 +4659,37 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
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cpu->phys_bits = 32;
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}
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}
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/* Cache information initialization */
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if (!cpu->legacy_cache) {
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if (!xcc->cpu_def || !xcc->cpu_def->cache_info) {
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char *name = x86_cpu_class_get_model_name(xcc);
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error_setg(errp,
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"CPU model '%s' doesn't support legacy-cache=off", name);
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g_free(name);
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return;
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}
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env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
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*xcc->cpu_def->cache_info;
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} else {
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/* Build legacy cache information */
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env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
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env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
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env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
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env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
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env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
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env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
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env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
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env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
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env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
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env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
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env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
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env->cache_info_amd.l3_cache = &legacy_l3_cache;
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}
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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@ -5173,11 +5173,10 @@ static Property x86_cpu_properties[] = {
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DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
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DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
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/*
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* lecacy_cache defaults to CPU model being chosen. This is set in
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* x86_cpu_load_def based on cache_info which is initialized in
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* builtin_x86_defs
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* lecacy_cache defaults to true unless the CPU model provides its
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* own cache information (see x86_cpu_load_def()).
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*/
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DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, false),
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DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
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/*
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* From "Requirements for Implementing the Microsoft
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@ -1098,10 +1098,10 @@ typedef struct CPUCacheInfo {
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typedef struct CPUCaches {
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CPUCacheInfo l1d_cache;
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CPUCacheInfo l1i_cache;
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CPUCacheInfo l2_cache;
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CPUCacheInfo l3_cache;
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CPUCacheInfo *l1d_cache;
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CPUCacheInfo *l1i_cache;
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CPUCacheInfo *l2_cache;
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CPUCacheInfo *l3_cache;
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} CPUCaches;
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typedef struct CPUX86State {
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@ -1293,7 +1293,11 @@ typedef struct CPUX86State {
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/* Features that were explicitly enabled/disabled */
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FeatureWordArray user_features;
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uint32_t cpuid_model[12];
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CPUCaches *cache_info;
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/* Cache information for CPUID. When legacy-cache=on, the cache data
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* on each CPUID leaf will be different, because we keep compatibility
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* with old QEMU versions.
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*/
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CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
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/* MTRRs */
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uint64_t mtrr_fixed[11];
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