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hw/arm_gic: Correctly restore nested irq priority

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Upon activating an interrupt, set the corresponding priority bit in the
APR/NSAPR registers without touching the currently set bits. In the event
of nested interrupts, the GIC will then have the information it needs to
restore the priority of the pre-empted interrupt once the higher priority
interrupt finishes execution.

Signed-off-by: François Baldassari <francois@pebble.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
François Baldassari 2015-11-19 12:09:52 +00:00 committed by Peter Maydell
parent 8f28030903
commit a859595791
1 changed files with 2 additions and 2 deletions
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4
hw/intc/arm_gic.c
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@ -254,9 +254,9 @@ static void gic_activate_irq(GICState *s, int cpu, int irq)
int bitno = preemption_level % 32;
if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) {
s->nsapr[regno][cpu] &= (1 << bitno);
s->nsapr[regno][cpu] |= (1 << bitno);
} else {
s->apr[regno][cpu] &= (1 << bitno);
s->apr[regno][cpu] |= (1 << bitno);
}
s->running_priority[cpu] = prio;