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target/arm: Implement vector shifted SCVF/UCVF for fp16
While we have some of the scalar paths for *CVF for fp16, we failed to decode the fp16 version of these instructions. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180502221552.3873-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -7405,13 +7405,26 @@ static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar,
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int immh, int immb, int opcode,
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int immh, int immb, int opcode,
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int rn, int rd)
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int rn, int rd)
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{
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{
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bool is_double = extract32(immh, 3, 1);
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int size, elements, fracbits;
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int size = is_double ? MO_64 : MO_32;
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int elements;
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int immhb = immh << 3 | immb;
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int immhb = immh << 3 | immb;
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int fracbits = (is_double ? 128 : 64) - immhb;
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if (!extract32(immh, 2, 2)) {
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if (immh & 8) {
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size = MO_64;
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if (!is_scalar && !is_q) {
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unallocated_encoding(s);
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return;
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}
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} else if (immh & 4) {
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size = MO_32;
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} else if (immh & 2) {
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size = MO_16;
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if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
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unallocated_encoding(s);
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return;
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}
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} else {
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/* immh == 0 would be a failure of the decode logic */
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g_assert(immh == 1);
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unallocated_encoding(s);
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unallocated_encoding(s);
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return;
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return;
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}
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}
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@ -7419,20 +7432,14 @@ static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar,
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if (is_scalar) {
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if (is_scalar) {
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elements = 1;
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elements = 1;
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} else {
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} else {
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elements = is_double ? 2 : is_q ? 4 : 2;
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elements = (8 << is_q) >> size;
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if (is_double && !is_q) {
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unallocated_encoding(s);
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return;
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}
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}
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}
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fracbits = (16 << size) - immhb;
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if (!fp_access_check(s)) {
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if (!fp_access_check(s)) {
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return;
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return;
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}
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}
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/* immh == 0 would be a failure of the decode logic */
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g_assert(immh);
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handle_simd_intfp_conv(s, rd, rn, elements, !is_u, fracbits, size);
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handle_simd_intfp_conv(s, rd, rn, elements, !is_u, fracbits, size);
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}
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}
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