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target/riscv: Tell gdbstub the correct number of CSRs

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If the number of registers reported to the gdbstub code does not match the
number in the associated XML file, then the register numbers used by the stub
may get out of sync with a remote GDB instance.

Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Jonathan Behrens 2019-10-14 11:45:27 -04:00 committed by Palmer Dabbelt
parent 2738b3b555
commit a555ad1399
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GPG Key ID: EF4CA1502CCBAB41
1 changed files with 2 additions and 2 deletions
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4
target/riscv/gdbstub.c
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@ -384,7 +384,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
}
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
4096, "riscv-32bit-csr.xml", 0);
240, "riscv-32bit-csr.xml", 0);
#elif defined(TARGET_RISCV64)
if (env->misa & RVF) {
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
@ -392,6 +392,6 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
}
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
4096, "riscv-64bit-csr.xml", 0);
240, "riscv-64bit-csr.xml", 0);
#endif
}