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hw/cxl: Update RAS Capability Definitions for version 3.

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Part of bringing all of CXL emulation inline with CXL r3.1.
No functional changes.

Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126121636.24611-4-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Jonathan Cameron 2024-01-26 12:16:34 +00:00 committed by Michael S. Tsirkin
parent 40ecac10c0
commit a185ff05fe
2 changed files with 5 additions and 2 deletions
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2
hw/cxl/cxl-component-utils.c
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@ -325,7 +325,7 @@ void cxl_component_register_init_common(uint32_t *reg_state,
CXL_##reg##_REGISTERS_OFFSET); \
} while (0)
init_cap_reg(RAS, 2, 2);
init_cap_reg(RAS, 2, CXL_RAS_CAPABILITY_VERSION);
ras_init_common(reg_state, write_msk);
init_cap_reg(LINK, 4, 2);

5
include/hw/cxl/cxl_component.h
View file

@ -60,8 +60,9 @@ CXLx_CAPABILITY_HEADER(SNOOP, 0x14)
* implements. Some of these are specific to certain types of components, but
* this implementation leaves enough space regardless.
*/
/* 8.2.5.9 - CXL RAS Capability Structure */
/* CXL r3.1 Section 8.2.4.17: CXL RAS Capability Structure */
#define CXL_RAS_CAPABILITY_VERSION 3
/* Give ample space for caps before this */
#define CXL_RAS_REGISTERS_OFFSET 0x80
#define CXL_RAS_REGISTERS_SIZE 0x58
@ -95,6 +96,8 @@ REG32(CXL_RAS_COR_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET + 0xc)
REG32(CXL_RAS_COR_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x10)
REG32(CXL_RAS_ERR_CAP_CTRL, CXL_RAS_REGISTERS_OFFSET + 0x14)
FIELD(CXL_RAS_ERR_CAP_CTRL, FIRST_ERROR_POINTER, 0, 6)
FIELD(CXL_RAS_ERR_CAP_CTRL, MULTIPLE_HEADER_RECORDING_CAP, 9, 1)
FIELD(CXL_RAS_ERR_POISON_ENABLED, POISON_ENABLED, 13, 1)
REG32(CXL_RAS_ERR_HEADER0, CXL_RAS_REGISTERS_OFFSET + 0x18)
#define CXL_RAS_ERR_HEADER_NUM 32
/* Offset 0x18 - 0x58 reserved for RAS logs */