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Add remaining PXA2xx on-chip peripherals except I2C master.

Browse source 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2751 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog 2007-04-30 01:48:07 +00:00
parent 2bac601963
commit a171fe394a
9 changed files with 2642 additions and 2 deletions
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32
hw/pxa.h
View file

@ -63,6 +63,12 @@
struct pxa2xx_pic_state_s;
qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
/* pxa2xx_timer.c */
void pxa25x_timer_init(target_phys_addr_t base,
qemu_irq *irqs, CPUState *cpustate);
void pxa27x_timer_init(target_phys_addr_t base,
qemu_irq *irqs, qemu_irq irq4, CPUState *cpustate);
/* pxa2xx_gpio.c */
struct pxa2xx_gpio_info_s;
struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
@ -81,6 +87,29 @@ struct pxa2xx_dma_state_s *pxa27x_dma_init(target_phys_addr_t base,
qemu_irq irq);
void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on);
/* pxa2xx_lcd.c */
struct pxa2xx_lcdc_s;
struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base,
qemu_irq irq, DisplayState *ds);
void pxa2xx_lcd_vsync_cb(struct pxa2xx_lcdc_s *s,
void (*cb)(void *opaque), void *opaque);
void pxa2xx_lcdc_oritentation(void *opaque, int angle);
/* pxa2xx_mmci.c */
struct pxa2xx_mmci_s;
struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
qemu_irq irq, void *dma);
void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, void *opaque,
void (*readonly_cb)(void *, int),
void (*coverswitch_cb)(void *, int));
/* pxa2xx_pcmcia.c */
struct pxa2xx_pcmcia_s;
struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base);
int pxa2xx_pcmcia_attach(void *opaque, struct pcmcia_card_s *card);
int pxa2xx_pcmcia_dettach(void *opaque);
void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
/* pxa2xx.c */
struct pxa2xx_ssp_s;
void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,
@ -95,7 +124,10 @@ struct pxa2xx_state_s {
qemu_irq *pic;
struct pxa2xx_dma_state_s *dma;
struct pxa2xx_gpio_info_s *gpio;
struct pxa2xx_lcdc_s *lcd;
struct pxa2xx_ssp_s **ssp;
struct pxa2xx_mmci_s *mmc;
struct pxa2xx_pcmcia_s *pcmcia[2];
struct pxa2xx_i2s_s *i2s;
struct pxa2xx_fir_s *fir;

29
hw/pxa2xx.c
View file

@ -1531,8 +1531,13 @@ struct pxa2xx_state_s *pxa270_init(DisplayState *ds, const char *revision)
s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
pxa27x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0],
s->pic[PXA27X_PIC_OST_4_11], s->env);
s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
s->mmc = pxa2xx_mmci_init(0x41100000, s->pic[PXA2XX_PIC_MMC], s->dma);
for (i = 0; pxa270_serial[i].io_base; i ++)
if (serial_hds[i])
serial_mm_init(pxa270_serial[i].io_base, 2,
@ -1543,6 +1548,9 @@ struct pxa2xx_state_s *pxa270_init(DisplayState *ds, const char *revision)
s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
s->dma, serial_hds[i]);
if (ds)
s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
s->cm_base = 0x41300000;
s->cm_regs[CCCR >> 4] = 0x02000210; /* 416.0 MHz */
s->clkcfg = 0x00000009; /* Turbo mode active */
@ -1575,6 +1583,13 @@ struct pxa2xx_state_s *pxa270_init(DisplayState *ds, const char *revision)
cpu_register_physical_memory(ssp[i].base, 0xfff, iomemtype);
}
if (usb_enabled) {
usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
}
s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
s->rtc_base = 0x40900000;
iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
pxa2xx_rtc_writefn, s);
@ -1609,8 +1624,12 @@ struct pxa2xx_state_s *pxa255_init(DisplayState *ds)
s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0], s->env);
s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
s->mmc = pxa2xx_mmci_init(0x41100000, s->pic[PXA2XX_PIC_MMC], s->dma);
for (i = 0; pxa255_serial[i].io_base; i ++)
if (serial_hds[i])
serial_mm_init(pxa255_serial[i].io_base, 2,
@ -1621,6 +1640,9 @@ struct pxa2xx_state_s *pxa255_init(DisplayState *ds)
s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
s->dma, serial_hds[i]);
if (ds)
s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
s->cm_base = 0x41300000;
s->cm_regs[CCCR >> 4] = 0x02000210; /* 416.0 MHz */
s->clkcfg = 0x00000009; /* Turbo mode active */
@ -1653,6 +1675,13 @@ struct pxa2xx_state_s *pxa255_init(DisplayState *ds)
cpu_register_physical_memory(ssp[i].base, 0xfff, iomemtype);
}
if (usb_enabled) {
usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
}
s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
s->rtc_base = 0x40900000;
iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
pxa2xx_rtc_writefn, s);

1001
hw/pxa2xx_lcd.c Normal file
View file

File diff suppressed because it is too large Load diff

472
hw/pxa2xx_mmci.c Normal file
View file

@ -0,0 +1,472 @@
/*
* Intel XScale PXA255/270 MultiMediaCard/SD/SDIO Controller emulation.
*
* Copyright (c) 2006 Openedhand Ltd.
* Written by Andrzej Zaborowski <balrog@zabor.org>
*
* This code is licensed under the GPLv2.
*/
#include "vl.h"
#include "sd.h"
struct pxa2xx_mmci_s {
target_phys_addr_t base;
qemu_irq irq;
void *dma;
SDState *card;
uint32_t status;
uint32_t clkrt;
uint32_t spi;
uint32_t cmdat;
uint32_t resp_tout;
uint32_t read_tout;
int blklen;
int numblk;
uint32_t intmask;
uint32_t intreq;
int cmd;
uint32_t arg;
int active;
int bytesleft;
uint8_t tx_fifo[64];
int tx_start;
int tx_len;
uint8_t rx_fifo[32];
int rx_start;
int rx_len;
uint16_t resp_fifo[9];
int resp_len;
int cmdreq;
int ac_width;
};
#define MMC_STRPCL 0x00 /* MMC Clock Start/Stop register */
#define MMC_STAT 0x04 /* MMC Status register */
#define MMC_CLKRT 0x08 /* MMC Clock Rate register */
#define MMC_SPI 0x0c /* MMC SPI Mode register */
#define MMC_CMDAT 0x10 /* MMC Command/Data register */
#define MMC_RESTO 0x14 /* MMC Response Time-Out register */
#define MMC_RDTO 0x18 /* MMC Read Time-Out register */
#define MMC_BLKLEN 0x1c /* MMC Block Length register */
#define MMC_NUMBLK 0x20 /* MMC Number of Blocks register */
#define MMC_PRTBUF 0x24 /* MMC Buffer Partly Full register */
#define MMC_I_MASK 0x28 /* MMC Interrupt Mask register */
#define MMC_I_REG 0x2c /* MMC Interrupt Request register */
#define MMC_CMD 0x30 /* MMC Command register */
#define MMC_ARGH 0x34 /* MMC Argument High register */
#define MMC_ARGL 0x38 /* MMC Argument Low register */
#define MMC_RES 0x3c /* MMC Response FIFO */
#define MMC_RXFIFO 0x40 /* MMC Receive FIFO */
#define MMC_TXFIFO 0x44 /* MMC Transmit FIFO */
#define MMC_RDWAIT 0x48 /* MMC RD_WAIT register */
#define MMC_BLKS_REM 0x4c /* MMC Blocks Remaining register */
/* Bitfield masks */
#define STRPCL_STOP_CLK (1 << 0)
#define STRPCL_STRT_CLK (1 << 1)
#define STAT_TOUT_RES (1 << 1)
#define STAT_CLK_EN (1 << 8)
#define STAT_DATA_DONE (1 << 11)
#define STAT_PRG_DONE (1 << 12)
#define STAT_END_CMDRES (1 << 13)
#define SPI_SPI_MODE (1 << 0)
#define CMDAT_RES_TYPE (3 << 0)
#define CMDAT_DATA_EN (1 << 2)
#define CMDAT_WR_RD (1 << 3)
#define CMDAT_DMA_EN (1 << 7)
#define CMDAT_STOP_TRAN (1 << 10)
#define INT_DATA_DONE (1 << 0)
#define INT_PRG_DONE (1 << 1)
#define INT_END_CMD (1 << 2)
#define INT_STOP_CMD (1 << 3)
#define INT_CLK_OFF (1 << 4)
#define INT_RXFIFO_REQ (1 << 5)
#define INT_TXFIFO_REQ (1 << 6)
#define INT_TINT (1 << 7)
#define INT_DAT_ERR (1 << 8)
#define INT_RES_ERR (1 << 9)
#define INT_RD_STALLED (1 << 10)
#define INT_SDIO_INT (1 << 11)
#define INT_SDIO_SACK (1 << 12)
#define PRTBUF_PRT_BUF (1 << 0)
/* Route internal interrupt lines to the global IC and DMA */
static void pxa2xx_mmci_int_update(struct pxa2xx_mmci_s *s)
{
uint32_t mask = s->intmask;
if (s->cmdat & CMDAT_DMA_EN) {
mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ;
pxa2xx_dma_request((struct pxa2xx_dma_state_s *) s->dma,
PXA2XX_RX_RQ_MMCI, !!(s->intreq & INT_RXFIFO_REQ));
pxa2xx_dma_request((struct pxa2xx_dma_state_s *) s->dma,
PXA2XX_TX_RQ_MMCI, !!(s->intreq & INT_TXFIFO_REQ));
}
qemu_set_irq(s->irq, !!(s->intreq & ~mask));
}
static void pxa2xx_mmci_fifo_update(struct pxa2xx_mmci_s *s)
{
if (!s->active)
return;
if (s->cmdat & CMDAT_WR_RD) {
while (s->bytesleft && s->tx_len) {
sd_write_data(s->card, s->tx_fifo[s->tx_start ++]);
s->tx_start &= 0x1f;
s->tx_len --;
s->bytesleft --;
}
if (s->bytesleft)
s->intreq |= INT_TXFIFO_REQ;
} else
while (s->bytesleft && s->rx_len < 32) {
s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
sd_read_data(s->card);
s->bytesleft --;
s->intreq |= INT_RXFIFO_REQ;
}
if (!s->bytesleft) {
s->active = 0;
s->intreq |= INT_DATA_DONE;
s->status |= STAT_DATA_DONE;
if (s->cmdat & CMDAT_WR_RD) {
s->intreq |= INT_PRG_DONE;
s->status |= STAT_PRG_DONE;
}
}
pxa2xx_mmci_int_update(s);
}
static void pxa2xx_mmci_wakequeues(struct pxa2xx_mmci_s *s)
{
int rsplen, i;
struct sd_request_s request;
uint8_t response[16];
s->active = 1;
s->rx_len = 0;
s->tx_len = 0;
s->cmdreq = 0;
request.cmd = s->cmd;
request.arg = s->arg;
request.crc = 0; /* FIXME */
rsplen = sd_do_command(s->card, &request, response);
s->intreq |= INT_END_CMD;
memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
switch (s->cmdat & CMDAT_RES_TYPE) {
#define PXAMMCI_RESP(wd, value0, value1) \
s->resp_fifo[(wd) + 0] |= (value0); \
s->resp_fifo[(wd) + 1] |= (value1) << 8;
case 0: /* No response */
goto complete;
case 1: /* R1, R4, R5 or R6 */
if (rsplen < 4)
goto timeout;
goto complete;
case 2: /* R2 */
if (rsplen < 16)
goto timeout;
goto complete;
case 3: /* R3 */
if (rsplen < 4)
goto timeout;
goto complete;
complete:
for (i = 0; rsplen > 0; i ++, rsplen -= 2) {
PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]);
}
s->status |= STAT_END_CMDRES;
if (!(s->cmdat & CMDAT_DATA_EN))
s->active = 0;
else
s->bytesleft = s->numblk * s->blklen;
s->resp_len = 0;
break;
timeout:
s->active = 0;
s->status |= STAT_TOUT_RES;
break;
}
pxa2xx_mmci_fifo_update(s);
}
static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset)
{
struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
uint32_t ret;
offset -= s->base;
switch (offset) {
case MMC_STRPCL:
return 0;
case MMC_STAT:
return s->status;
case MMC_CLKRT:
return s->clkrt;
case MMC_SPI:
return s->spi;
case MMC_CMDAT:
return s->cmdat;
case MMC_RESTO:
return s->resp_tout;
case MMC_RDTO:
return s->read_tout;
case MMC_BLKLEN:
return s->blklen;
case MMC_NUMBLK:
return s->numblk;
case MMC_PRTBUF:
return 0;
case MMC_I_MASK:
return s->intmask;
case MMC_I_REG:
return s->intreq;
case MMC_CMD:
return s->cmd | 0x40;
case MMC_ARGH:
return s->arg >> 16;
case MMC_ARGL:
return s->arg & 0xffff;
case MMC_RES:
if (s->resp_len < 9)
return s->resp_fifo[s->resp_len ++];
return 0;
case MMC_RXFIFO:
ret = 0;
while (s->ac_width -- && s->rx_len) {
ret |= s->rx_fifo[s->rx_start ++] << (s->ac_width << 3);
s->rx_start &= 0x1f;
s->rx_len --;
}
s->intreq &= ~INT_RXFIFO_REQ;
pxa2xx_mmci_fifo_update(s);
return ret;
case MMC_RDWAIT:
return 0;
case MMC_BLKS_REM:
return s->numblk;
default:
cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n",
__FUNCTION__, offset);
}
return 0;
}
static void pxa2xx_mmci_write(void *opaque,
target_phys_addr_t offset, uint32_t value)
{
struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
offset -= s->base;
switch (offset) {
case MMC_STRPCL:
if (value & STRPCL_STRT_CLK) {
s->status |= STAT_CLK_EN;
s->intreq &= ~INT_CLK_OFF;
if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) {
s->status &= STAT_CLK_EN;
pxa2xx_mmci_wakequeues(s);
}
}
if (value & STRPCL_STOP_CLK) {
s->status &= ~STAT_CLK_EN;
s->intreq |= INT_CLK_OFF;
s->active = 0;
}
pxa2xx_mmci_int_update(s);
break;
case MMC_CLKRT:
s->clkrt = value & 7;
break;
case MMC_SPI:
s->spi = value & 0xf;
if (value & SPI_SPI_MODE)
printf("%s: attempted to use card in SPI mode\n", __FUNCTION__);
break;
case MMC_CMDAT:
s->cmdat = value & 0x3dff;
s->active = 0;
s->cmdreq = 1;
if (!(value & CMDAT_STOP_TRAN)) {
s->status &= STAT_CLK_EN;
if (s->status & STAT_CLK_EN)
pxa2xx_mmci_wakequeues(s);
}
pxa2xx_mmci_int_update(s);
break;
case MMC_RESTO:
s->resp_tout = value & 0x7f;
break;
case MMC_RDTO:
s->read_tout = value & 0xffff;
break;
case MMC_BLKLEN:
s->blklen = value & 0xfff;
break;
case MMC_NUMBLK:
s->numblk = value & 0xffff;
break;
case MMC_PRTBUF:
if (value & PRTBUF_PRT_BUF) {
s->tx_start ^= 32;
s->tx_len = 0;
}
pxa2xx_mmci_fifo_update(s);
break;
case MMC_I_MASK:
s->intmask = value & 0x1fff;
pxa2xx_mmci_int_update(s);
break;
case MMC_CMD:
s->cmd = value & 0x3f;
break;
case MMC_ARGH:
s->arg &= 0x0000ffff;
s->arg |= value << 16;
break;
case MMC_ARGL:
s->arg &= 0xffff0000;
s->arg |= value & 0x0000ffff;
break;
case MMC_TXFIFO:
while (s->ac_width -- && s->tx_len < 0x20)
s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
(value >> (s->ac_width << 3)) & 0xff;
s->intreq &= ~INT_TXFIFO_REQ;
pxa2xx_mmci_fifo_update(s);
break;
case MMC_RDWAIT:
case MMC_BLKS_REM:
break;
default:
cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n",
__FUNCTION__, offset);
}
}
static uint32_t pxa2xx_mmci_readb(void *opaque, target_phys_addr_t offset)
{
struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
s->ac_width = 1;
return pxa2xx_mmci_read(opaque, offset);
}
static uint32_t pxa2xx_mmci_readh(void *opaque, target_phys_addr_t offset)
{
struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
s->ac_width = 2;
return pxa2xx_mmci_read(opaque, offset);
}
static uint32_t pxa2xx_mmci_readw(void *opaque, target_phys_addr_t offset)
{
struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
s->ac_width = 4;
return pxa2xx_mmci_read(opaque, offset);
}
static CPUReadMemoryFunc *pxa2xx_mmci_readfn[] = {
pxa2xx_mmci_readb,
pxa2xx_mmci_readh,
pxa2xx_mmci_readw
};
static void pxa2xx_mmci_writeb(void *opaque,
target_phys_addr_t offset, uint32_t value)
{
struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
s->ac_width = 1;
pxa2xx_mmci_write(opaque, offset, value);
}
static void pxa2xx_mmci_writeh(void *opaque,
target_phys_addr_t offset, uint32_t value)
{
struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
s->ac_width = 2;
pxa2xx_mmci_write(opaque, offset, value);
}
static void pxa2xx_mmci_writew(void *opaque,
target_phys_addr_t offset, uint32_t value)
{
struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
s->ac_width = 4;
pxa2xx_mmci_write(opaque, offset, value);
}
static CPUWriteMemoryFunc *pxa2xx_mmci_writefn[] = {
pxa2xx_mmci_writeb,
pxa2xx_mmci_writeh,
pxa2xx_mmci_writew
};
struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
qemu_irq irq, void *dma)
{
int iomemtype;
struct pxa2xx_mmci_s *s;
s = (struct pxa2xx_mmci_s *) qemu_mallocz(sizeof(struct pxa2xx_mmci_s));
s->base = base;
s->irq = irq;
s->dma = dma;
iomemtype = cpu_register_io_memory(0, pxa2xx_mmci_readfn,
pxa2xx_mmci_writefn, s);
cpu_register_physical_memory(base, 0x000fffff, iomemtype);
/* Instantiate the actual storage */
s->card = sd_init(sd_bdrv);
return s;
}
void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, void *opaque,
void (*readonly_cb)(void *, int),
void (*coverswitch_cb)(void *, int))
{
sd_set_cb(s->card, opaque, readonly_cb, coverswitch_cb);
}

224
hw/pxa2xx_pcmcia.c Normal file
View file

@ -0,0 +1,224 @@
/*
* Intel XScale PXA255/270 PC Card and CompactFlash Interface.
*
* Copyright (c) 2006 Openedhand Ltd.
* Written by Andrzej Zaborowski <balrog@zabor.org>
*
* This code is licensed under the GPLv2.
*/
#include "vl.h"
struct pxa2xx_pcmcia_s {
struct pcmcia_socket_s slot;
struct pcmcia_card_s *card;
target_phys_addr_t common_base;
target_phys_addr_t attr_base;
target_phys_addr_t io_base;
qemu_irq irq;
qemu_irq cd_irq;
};
static uint32_t pxa2xx_pcmcia_common_read(void *opaque,
target_phys_addr_t offset)
{
struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
if (s->slot.attached) {
offset -= s->common_base;
return s->card->common_read(s->card->state, offset);
}
return 0;
}
static void pxa2xx_pcmcia_common_write(void *opaque,
target_phys_addr_t offset, uint32_t value)
{
struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
if (s->slot.attached) {
offset -= s->common_base;
s->card->common_write(s->card->state, offset, value);
}
}
static uint32_t pxa2xx_pcmcia_attr_read(void *opaque,
target_phys_addr_t offset)
{
struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
if (s->slot.attached) {
offset -= s->attr_base;
return s->card->attr_read(s->card->state, offset);
}
return 0;
}
static void pxa2xx_pcmcia_attr_write(void *opaque,
target_phys_addr_t offset, uint32_t value)
{
struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
if (s->slot.attached) {
offset -= s->attr_base;
s->card->attr_write(s->card->state, offset, value);
}
}
static uint32_t pxa2xx_pcmcia_io_read(void *opaque,
target_phys_addr_t offset)
{
struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
if (s->slot.attached) {
offset -= s->io_base;
return s->card->io_read(s->card->state, offset);
}
return 0;
}
static void pxa2xx_pcmcia_io_write(void *opaque,
target_phys_addr_t offset, uint32_t value)
{
struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
if (s->slot.attached) {
offset -= s->io_base;
s->card->io_write(s->card->state, offset, value);
}
}
static CPUReadMemoryFunc *pxa2xx_pcmcia_common_readfn[] = {
pxa2xx_pcmcia_common_read,
pxa2xx_pcmcia_common_read,
pxa2xx_pcmcia_common_read,
};
static CPUWriteMemoryFunc *pxa2xx_pcmcia_common_writefn[] = {
pxa2xx_pcmcia_common_write,
pxa2xx_pcmcia_common_write,
pxa2xx_pcmcia_common_write,
};
static CPUReadMemoryFunc *pxa2xx_pcmcia_attr_readfn[] = {
pxa2xx_pcmcia_attr_read,
pxa2xx_pcmcia_attr_read,
pxa2xx_pcmcia_attr_read,
};
static CPUWriteMemoryFunc *pxa2xx_pcmcia_attr_writefn[] = {
pxa2xx_pcmcia_attr_write,
pxa2xx_pcmcia_attr_write,
pxa2xx_pcmcia_attr_write,
};
static CPUReadMemoryFunc *pxa2xx_pcmcia_io_readfn[] = {
pxa2xx_pcmcia_io_read,
pxa2xx_pcmcia_io_read,
pxa2xx_pcmcia_io_read,
};
static CPUWriteMemoryFunc *pxa2xx_pcmcia_io_writefn[] = {
pxa2xx_pcmcia_io_write,
pxa2xx_pcmcia_io_write,
pxa2xx_pcmcia_io_write,
};
static void pxa2xx_pcmcia_set_irq(void *opaque, int line, int level)
{
struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
if (!s->irq)
return;
qemu_set_irq(s->irq, level);
}
struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base)
{
int iomemtype;
struct pxa2xx_pcmcia_s *s;
s = (struct pxa2xx_pcmcia_s *)
qemu_mallocz(sizeof(struct pxa2xx_pcmcia_s));
/* Socket I/O Memory Space */
s->io_base = base | 0x00000000;
iomemtype = cpu_register_io_memory(0, pxa2xx_pcmcia_io_readfn,
pxa2xx_pcmcia_io_writefn, s);
cpu_register_physical_memory(s->io_base, 0x03ffffff, iomemtype);
/* Then next 64 MB is reserved */
/* Socket Attribute Memory Space */
s->attr_base = base | 0x08000000;
iomemtype = cpu_register_io_memory(0, pxa2xx_pcmcia_attr_readfn,
pxa2xx_pcmcia_attr_writefn, s);
cpu_register_physical_memory(s->attr_base, 0x03ffffff, iomemtype);
/* Socket Common Memory Space */
s->common_base = base | 0x0c000000;
iomemtype = cpu_register_io_memory(0, pxa2xx_pcmcia_common_readfn,
pxa2xx_pcmcia_common_writefn, s);
cpu_register_physical_memory(s->common_base, 0x03ffffff, iomemtype);
if (base == 0x30000000)
s->slot.slot_string = "PXA PC Card Socket 1";
else
s->slot.slot_string = "PXA PC Card Socket 0";
s->slot.irq = qemu_allocate_irqs(pxa2xx_pcmcia_set_irq, s, 1)[0];
pcmcia_socket_register(&s->slot);
return s;
}
/* Insert a new card into a slot */
int pxa2xx_pcmcia_attach(void *opaque, struct pcmcia_card_s *card)
{
struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
if (s->slot.attached)
return -EEXIST;
if (s->cd_irq) {
qemu_irq_raise(s->cd_irq);
}
s->card = card;
s->slot.attached = 1;
s->card->slot = &s->slot;
s->card->attach(s->card->state);
return 0;
}
/* Eject card from the slot */
int pxa2xx_pcmcia_dettach(void *opaque)
{
struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
if (!s->slot.attached)
return -ENOENT;
s->card->detach(s->card->state);
s->card->slot = 0;
s->card = 0;
s->slot.attached = 0;
if (s->irq)
qemu_irq_lower(s->irq);
if (s->cd_irq)
qemu_irq_lower(s->cd_irq);
return 0;
}
/* Who to notify on card events */
void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq)
{
struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
s->irq = irq;
s->cd_irq = cd_irq;
}

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/*
* Intel XScale PXA255/270 LCDC emulation.
*
* Copyright (c) 2006 Openedhand Ltd.
* Written by Andrzej Zaborowski <balrog@zabor.org>
*
* This code is licensed under the GPLv2.
*
* Framebuffer format conversion routines.
*/
# define SKIP_PIXEL(to) to += deststep
#if BITS == 8
# define COPY_PIXEL(to, from) *to = from; SKIP_PIXEL(to)
#elif BITS == 15 || BITS == 16
# define COPY_PIXEL(to, from) *(uint16_t *) to = from; SKIP_PIXEL(to)
#elif BITS == 24
# define COPY_PIXEL(to, from) \
*(uint16_t *) to = from; *(to + 2) = (from) >> 16; SKIP_PIXEL(to)
#elif BITS == 32
# define COPY_PIXEL(to, from) *(uint32_t *) to = from; SKIP_PIXEL(to)
#else
# error unknown bit depth
#endif
#ifdef WORDS_BIGENDIAN
# define SWAP_WORDS 1
#endif
#define FN_2(x) FN(x + 1) FN(x)
#define FN_4(x) FN_2(x + 2) FN_2(x)
static void glue(pxa2xx_draw_line2_, BITS)(uint32_t *palette,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t data;
while (width > 0) {
data = *(uint32_t *) src;
#define FN(x) COPY_PIXEL(dest, palette[(data >> ((x) * 2)) & 3]);
#ifdef SWAP_WORDS
FN_4(12)
FN_4(8)
FN_4(4)
FN_4(0)
#else
FN_4(0)
FN_4(4)
FN_4(8)
FN_4(12)
#endif
#undef FN
width -= 16;
src += 4;
}
}
static void glue(pxa2xx_draw_line4_, BITS)(uint32_t *palette,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t data;
while (width > 0) {
data = *(uint32_t *) src;
#define FN(x) COPY_PIXEL(dest, palette[(data >> ((x) * 4)) & 0xf]);
#ifdef SWAP_WORDS
FN_2(6)
FN_2(4)
FN_2(2)
FN_2(0)
#else
FN_2(0)
FN_2(2)
FN_2(4)
FN_2(6)
#endif
#undef FN
width -= 8;
src += 4;
}
}
static void glue(pxa2xx_draw_line8_, BITS)(uint32_t *palette,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t data;
while (width > 0) {
data = *(uint32_t *) src;
#define FN(x) COPY_PIXEL(dest, palette[(data >> (x)) & 0xff]);
#ifdef SWAP_WORDS
FN(24)
FN(16)
FN(8)
FN(0)
#else
FN(0)
FN(8)
FN(16)
FN(24)
#endif
#undef FN
width -= 4;
src += 4;
}
}
static void glue(pxa2xx_draw_line16_, BITS)(uint32_t *palette,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t data;
unsigned int r, g, b;
while (width > 0) {
data = *(uint32_t *) src;
#ifdef SWAP_WORDS
data = bswap32(data);
#endif
b = (data & 0x1f) << 3;
data >>= 5;
g = (data & 0x3f) << 2;
data >>= 6;
r = (data & 0x1f) << 3;
data >>= 5;
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
b = (data & 0x1f) << 3;
data >>= 5;
g = (data & 0x3f) << 2;
data >>= 6;
r = (data & 0x1f) << 3;
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
width -= 2;
src += 4;
}
}
static void glue(pxa2xx_draw_line16t_, BITS)(uint32_t *palette,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t data;
unsigned int r, g, b;
while (width > 0) {
data = *(uint32_t *) src;
#ifdef SWAP_WORDS
data = bswap32(data);
#endif
b = (data & 0x1f) << 3;
data >>= 5;
g = (data & 0x1f) << 3;
data >>= 5;
r = (data & 0x1f) << 3;
data >>= 5;
if (data & 1)
SKIP_PIXEL(dest);
else
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
data >>= 1;
b = (data & 0x1f) << 3;
data >>= 5;
g = (data & 0x1f) << 3;
data >>= 5;
r = (data & 0x1f) << 3;
if (data & 1)
SKIP_PIXEL(dest);
else
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
width -= 2;
src += 4;
}
}
static void glue(pxa2xx_draw_line18_, BITS)(uint32_t *palette,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t data;
unsigned int r, g, b;
while (width > 0) {
data = *(uint32_t *) src;
#ifdef SWAP_WORDS
data = bswap32(data);
#endif
b = (data & 0x3f) << 2;
data >>= 6;
g = (data & 0x3f) << 2;
data >>= 6;
r = (data & 0x3f) << 2;
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
width -= 1;
src += 4;
}
}
/* The wicked packed format */
static void glue(pxa2xx_draw_line18p_, BITS)(uint32_t *palette,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t data[3];
unsigned int r, g, b;
while (width > 0) {
data[0] = *(uint32_t *) src;
src += 4;
data[1] = *(uint32_t *) src;
src += 4;
data[2] = *(uint32_t *) src;
src += 4;
#ifdef SWAP_WORDS
data[0] = bswap32(data[0]);
data[1] = bswap32(data[1]);
data[2] = bswap32(data[2]);
#endif
b = (data[0] & 0x3f) << 2;
data[0] >>= 6;
g = (data[0] & 0x3f) << 2;
data[0] >>= 6;
r = (data[0] & 0x3f) << 2;
data[0] >>= 12;
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
b = (data[0] & 0x3f) << 2;
data[0] >>= 6;
g = ((data[1] & 0xf) << 4) | (data[0] << 2);
data[1] >>= 4;
r = (data[1] & 0x3f) << 2;
data[1] >>= 12;
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
b = (data[1] & 0x3f) << 2;
data[1] >>= 6;
g = (data[1] & 0x3f) << 2;
data[1] >>= 6;
r = ((data[2] & 0x3) << 6) | (data[1] << 2);
data[2] >>= 8;
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
b = (data[2] & 0x3f) << 2;
data[2] >>= 6;
g = (data[2] & 0x3f) << 2;
data[2] >>= 6;
r = data[2] << 2;
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
width -= 4;
}
}
static void glue(pxa2xx_draw_line19_, BITS)(uint32_t *palette,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t data;
unsigned int r, g, b;
while (width > 0) {
data = *(uint32_t *) src;
#ifdef SWAP_WORDS
data = bswap32(data);
#endif
b = (data & 0x3f) << 2;
data >>= 6;
g = (data & 0x3f) << 2;
data >>= 6;
r = (data & 0x3f) << 2;
data >>= 6;
if (data & 1)
SKIP_PIXEL(dest);
else
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
width -= 1;
src += 4;
}
}
/* The wicked packed format */
static void glue(pxa2xx_draw_line19p_, BITS)(uint32_t *palette,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t data[3];
unsigned int r, g, b;
while (width > 0) {
data[0] = *(uint32_t *) src;
src += 4;
data[1] = *(uint32_t *) src;
src += 4;
data[2] = *(uint32_t *) src;
src += 4;
# ifdef SWAP_WORDS
data[0] = bswap32(data[0]);
data[1] = bswap32(data[1]);
data[2] = bswap32(data[2]);
# endif
b = (data[0] & 0x3f) << 2;
data[0] >>= 6;
g = (data[0] & 0x3f) << 2;
data[0] >>= 6;
r = (data[0] & 0x3f) << 2;
data[0] >>= 6;
if (data[0] & 1)
SKIP_PIXEL(dest);
else
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
data[0] >>= 6;
b = (data[0] & 0x3f) << 2;
data[0] >>= 6;
g = ((data[1] & 0xf) << 4) | (data[0] << 2);
data[1] >>= 4;
r = (data[1] & 0x3f) << 2;
data[1] >>= 6;
if (data[1] & 1)
SKIP_PIXEL(dest);
else
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
data[1] >>= 6;
b = (data[1] & 0x3f) << 2;
data[1] >>= 6;
g = (data[1] & 0x3f) << 2;
data[1] >>= 6;
r = ((data[2] & 0x3) << 6) | (data[1] << 2);
data[2] >>= 2;
if (data[2] & 1)
SKIP_PIXEL(dest);
else
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
data[2] >>= 6;
b = (data[2] & 0x3f) << 2;
data[2] >>= 6;
g = (data[2] & 0x3f) << 2;
data[2] >>= 6;
r = data[2] << 2;
data[2] >>= 6;
if (data[2] & 1)
SKIP_PIXEL(dest);
else
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
width -= 4;
}
}
static void glue(pxa2xx_draw_line24_, BITS)(uint32_t *palette,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t data;
unsigned int r, g, b;
while (width > 0) {
data = *(uint32_t *) src;
#ifdef SWAP_WORDS
data = bswap32(data);
#endif
b = data & 0xff;
data >>= 8;
g = data & 0xff;
data >>= 8;
r = data & 0xff;
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
width -= 1;
src += 4;
}
}
static void glue(pxa2xx_draw_line24t_, BITS)(uint32_t *palette,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t data;
unsigned int r, g, b;
while (width > 0) {
data = *(uint32_t *) src;
#ifdef SWAP_WORDS
data = bswap32(data);
#endif
b = (data & 0x7f) << 1;
data >>= 7;
g = data & 0xff;
data >>= 8;
r = data & 0xff;
data >>= 8;
if (data & 1)
SKIP_PIXEL(dest);
else
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
width -= 1;
src += 4;
}
}
static void glue(pxa2xx_draw_line25_, BITS)(uint32_t *palette,
uint8_t *dest, const uint8_t *src, int width, int deststep)
{
uint32_t data;
unsigned int r, g, b;
while (width > 0) {
data = *(uint32_t *) src;
#ifdef SWAP_WORDS
data = bswap32(data);
#endif
b = data & 0xff;
data >>= 8;
g = data & 0xff;
data >>= 8;
r = data & 0xff;
data >>= 8;
if (data & 1)
SKIP_PIXEL(dest);
else
COPY_PIXEL(dest, glue(rgb_to_pixel, BITS)(r, g, b));
width -= 1;
src += 4;
}
}
/* Overlay planes disabled, no transparency */
static drawfn glue(pxa2xx_draw_fn_, BITS)[16] =
{
[0 ... 0xf] = 0,
[pxa_lcdc_2bpp] = glue(pxa2xx_draw_line2_, BITS),
[pxa_lcdc_4bpp] = glue(pxa2xx_draw_line4_, BITS),
[pxa_lcdc_8bpp] = glue(pxa2xx_draw_line8_, BITS),
[pxa_lcdc_16bpp] = glue(pxa2xx_draw_line16_, BITS),
[pxa_lcdc_18bpp] = glue(pxa2xx_draw_line18_, BITS),
[pxa_lcdc_18pbpp] = glue(pxa2xx_draw_line18p_, BITS),
[pxa_lcdc_24bpp] = glue(pxa2xx_draw_line24_, BITS),
};
/* Overlay planes enabled, transparency used */
static drawfn glue(glue(pxa2xx_draw_fn_, BITS), t)[16] =
{
[0 ... 0xf] = 0,
[pxa_lcdc_4bpp] = glue(pxa2xx_draw_line4_, BITS),
[pxa_lcdc_8bpp] = glue(pxa2xx_draw_line8_, BITS),
[pxa_lcdc_16bpp] = glue(pxa2xx_draw_line16t_, BITS),
[pxa_lcdc_19bpp] = glue(pxa2xx_draw_line19_, BITS),
[pxa_lcdc_19pbpp] = glue(pxa2xx_draw_line19p_, BITS),
[pxa_lcdc_24bpp] = glue(pxa2xx_draw_line24t_, BITS),
[pxa_lcdc_25bpp] = glue(pxa2xx_draw_line25_, BITS),
};
#undef BITS
#undef COPY_PIXEL
#undef SKIP_PIXEL
#ifdef SWAP_WORDS
# undef SWAP_WORDS
#endif

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/*
* Intel XScale PXA255/270 OS Timers.
*
* Copyright (c) 2006 Openedhand Ltd.
* Copyright (c) 2006 Thorsten Zitterell
*
* This code is licenced under the GPL.
*/
#include "vl.h"
#define OSMR0 0x00
#define OSMR1 0x04
#define OSMR2 0x08
#define OSMR3 0x0c
#define OSMR4 0x80
#define OSMR5 0x84
#define OSMR6 0x88
#define OSMR7 0x8c
#define OSMR8 0x90
#define OSMR9 0x94
#define OSMR10 0x98
#define OSMR11 0x9c
#define OSCR 0x10 /* OS Timer Count */
#define OSCR4 0x40
#define OSCR5 0x44
#define OSCR6 0x48
#define OSCR7 0x4c
#define OSCR8 0x50
#define OSCR9 0x54
#define OSCR10 0x58
#define OSCR11 0x5c
#define OSSR 0x14 /* Timer status register */
#define OWER 0x18
#define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
#define OMCR4 0xc0 /* OS Match Control registers */
#define OMCR5 0xc4
#define OMCR6 0xc8
#define OMCR7 0xcc
#define OMCR8 0xd0
#define OMCR9 0xd4
#define OMCR10 0xd8
#define OMCR11 0xdc
#define OSNR 0x20
#define PXA25X_FREQ 3686400 /* 3.6864 MHz */
#define PXA27X_FREQ 3250000 /* 3.25 MHz */
static int pxa2xx_timer4_freq[8] = {
[0] = 0,
[1] = 32768,
[2] = 1000,
[3] = 1,
[4] = 1000000,
/* [5] is the "Externally supplied clock". Assign if necessary. */
[5 ... 7] = 0,
};
struct pxa2xx_timer0_s {
uint32_t value;
int level;
qemu_irq irq;
QEMUTimer *qtimer;
int num;
void *info;
};
struct pxa2xx_timer4_s {
uint32_t value;
int level;
qemu_irq irq;
QEMUTimer *qtimer;
int num;
void *info;
int32_t oldclock;
int32_t clock;
uint64_t lastload;
uint32_t freq;
uint32_t control;
};
typedef struct {
uint32_t base;
int32_t clock;
int32_t oldclock;
uint64_t lastload;
uint32_t freq;
struct pxa2xx_timer0_s timer[4];
struct pxa2xx_timer4_s *tm4;
uint32_t events;
uint32_t irq_enabled;
uint32_t reset3;
CPUState *cpustate;
int64_t qemu_ticks;
uint32_t snapshot;
} pxa2xx_timer_info;
static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
{
pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
int i;
uint32_t now_vm;
uint64_t new_qemu;
now_vm = s->clock +
muldiv64(now_qemu - s->lastload, s->freq, ticks_per_sec);
for (i = 0; i < 4; i ++) {
new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
ticks_per_sec, s->freq);
qemu_mod_timer(s->timer[i].qtimer, new_qemu);
}
}
static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
{
pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
uint32_t now_vm;
uint64_t new_qemu;
static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
int counter;
if (s->tm4[n].control & (1 << 7))
counter = n;
else
counter = counters[n];
if (!s->tm4[counter].freq) {
qemu_del_timer(s->timer[n].qtimer);
return;
}
now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
s->tm4[counter].lastload,
s->tm4[counter].freq, ticks_per_sec);
new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].value - now_vm),
ticks_per_sec, s->tm4[counter].freq);
qemu_mod_timer(s->timer[n].qtimer, new_qemu);
}
static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset)
{
pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
int tm = 0;
offset -= s->base;
switch (offset) {
case OSMR3: tm ++;
case OSMR2: tm ++;
case OSMR1: tm ++;
case OSMR0:
return s->timer[tm].value;
case OSMR11: tm ++;
case OSMR10: tm ++;
case OSMR9: tm ++;
case OSMR8: tm ++;
case OSMR7: tm ++;
case OSMR6: tm ++;
case OSMR5: tm ++;
case OSMR4:
if (!s->tm4)
goto badreg;
return s->tm4[tm].value;
case OSCR:
return s->clock + muldiv64(qemu_get_clock(vm_clock) -
s->lastload, s->freq, ticks_per_sec);
case OSCR11: tm ++;
case OSCR10: tm ++;
case OSCR9: tm ++;
case OSCR8: tm ++;
case OSCR7: tm ++;
case OSCR6: tm ++;
case OSCR5: tm ++;
case OSCR4:
if (!s->tm4)
goto badreg;
if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
if (s->tm4[tm - 1].freq)
s->snapshot = s->tm4[tm - 1].clock + muldiv64(
qemu_get_clock(vm_clock) -
s->tm4[tm - 1].lastload,
s->tm4[tm - 1].freq, ticks_per_sec);
else
s->snapshot = s->tm4[tm - 1].clock;
}
if (!s->tm4[tm].freq)
return s->tm4[tm].clock;
return s->tm4[tm].clock + muldiv64(qemu_get_clock(vm_clock) -
s->tm4[tm].lastload, s->tm4[tm].freq, ticks_per_sec);
case OIER:
return s->irq_enabled;
case OSSR: /* Status register */
return s->events;
case OWER:
return s->reset3;
case OMCR11: tm ++;
case OMCR10: tm ++;
case OMCR9: tm ++;
case OMCR8: tm ++;
case OMCR7: tm ++;
case OMCR6: tm ++;
case OMCR5: tm ++;
case OMCR4:
if (!s->tm4)
goto badreg;
return s->tm4[tm].control;
case OSNR:
return s->snapshot;
default:
badreg:
cpu_abort(cpu_single_env, "pxa2xx_timer_read: Bad offset "
REG_FMT "\n", offset);
}
return 0;
}
static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
int i, tm = 0;
pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
offset -= s->base;
switch (offset) {
case OSMR3: tm ++;
case OSMR2: tm ++;
case OSMR1: tm ++;
case OSMR0:
s->timer[tm].value = value;
pxa2xx_timer_update(s, qemu_get_clock(vm_clock));
break;
case OSMR11: tm ++;
case OSMR10: tm ++;
case OSMR9: tm ++;
case OSMR8: tm ++;
case OSMR7: tm ++;
case OSMR6: tm ++;
case OSMR5: tm ++;
case OSMR4:
if (!s->tm4)
goto badreg;
s->tm4[tm].value = value;
pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
break;
case OSCR:
s->oldclock = s->clock;
s->lastload = qemu_get_clock(vm_clock);
s->clock = value;
pxa2xx_timer_update(s, s->lastload);
break;
case OSCR11: tm ++;
case OSCR10: tm ++;
case OSCR9: tm ++;
case OSCR8: tm ++;
case OSCR7: tm ++;
case OSCR6: tm ++;
case OSCR5: tm ++;
case OSCR4:
if (!s->tm4)
goto badreg;
s->tm4[tm].oldclock = s->tm4[tm].clock;
s->tm4[tm].lastload = qemu_get_clock(vm_clock);
s->tm4[tm].clock = value;
pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
break;
case OIER:
s->irq_enabled = value & 0xfff;
break;
case OSSR: /* Status register */
s->events &= ~value;
for (i = 0; i < 4; i ++, value >>= 1) {
if (s->timer[i].level && (value & 1)) {
s->timer[i].level = 0;
qemu_irq_lower(s->timer[i].irq);
}
}
if (s->tm4) {
for (i = 0; i < 8; i ++, value >>= 1)
if (s->tm4[i].level && (value & 1))
s->tm4[i].level = 0;
if (!(s->events & 0xff0))
qemu_irq_lower(s->tm4->irq);
}
break;
case OWER: /* XXX: Reset on OSMR3 match? */
s->reset3 = value;
break;
case OMCR7: tm ++;
case OMCR6: tm ++;
case OMCR5: tm ++;
case OMCR4:
if (!s->tm4)
goto badreg;
s->tm4[tm].control = value & 0x0ff;
/* XXX Stop if running (shouldn't happen) */
if ((value & (1 << 7)) || tm == 0)
s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
else {
s->tm4[tm].freq = 0;
pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
}
break;
case OMCR11: tm ++;
case OMCR10: tm ++;
case OMCR9: tm ++;
case OMCR8: tm += 4;
if (!s->tm4)
goto badreg;
s->tm4[tm].control = value & 0x3ff;
/* XXX Stop if running (shouldn't happen) */
if ((value & (1 << 7)) || !(tm & 1))
s->tm4[tm].freq =
pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)];
else {
s->tm4[tm].freq = 0;
pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
}
break;
default:
badreg:
cpu_abort(cpu_single_env, "pxa2xx_timer_write: Bad offset "
REG_FMT "\n", offset);
}
}
static CPUReadMemoryFunc *pxa2xx_timer_readfn[] = {
pxa2xx_timer_read,
pxa2xx_timer_read,
pxa2xx_timer_read,
};
static CPUWriteMemoryFunc *pxa2xx_timer_writefn[] = {
pxa2xx_timer_write,
pxa2xx_timer_write,
pxa2xx_timer_write,
};
static void pxa2xx_timer_tick(void *opaque)
{
struct pxa2xx_timer0_s *t = (struct pxa2xx_timer0_s *) opaque;
pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->info;
if (i->irq_enabled & (1 << t->num)) {
t->level = 1;
i->events |= 1 << t->num;
qemu_irq_raise(t->irq);
}
if (t->num == 3)
if (i->reset3 & 1) {
i->reset3 = 0;
cpu_reset(i->cpustate);
}
}
static void pxa2xx_timer_tick4(void *opaque)
{
struct pxa2xx_timer4_s *t = (struct pxa2xx_timer4_s *) opaque;
pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->info;
pxa2xx_timer_tick4(opaque);
if (t->control & (1 << 3))
t->clock = 0;
if (t->control & (1 << 6))
pxa2xx_timer_update4(i, qemu_get_clock(vm_clock), t->num - 4);
}
static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
qemu_irq *irqs, CPUState *cpustate)
{
int i;
int iomemtype;
pxa2xx_timer_info *s;
s = (pxa2xx_timer_info *) qemu_mallocz(sizeof(pxa2xx_timer_info));
s->base = base;
s->irq_enabled = 0;
s->oldclock = 0;
s->clock = 0;
s->lastload = qemu_get_clock(vm_clock);
s->reset3 = 0;
s->cpustate = cpustate;
for (i = 0; i < 4; i ++) {
s->timer[i].value = 0;
s->timer[i].irq = irqs[i];
s->timer[i].info = s;
s->timer[i].num = i;
s->timer[i].level = 0;
s->timer[i].qtimer = qemu_new_timer(vm_clock,
pxa2xx_timer_tick, &s->timer[i]);
}
iomemtype = cpu_register_io_memory(0, pxa2xx_timer_readfn,
pxa2xx_timer_writefn, s);
cpu_register_physical_memory(base, 0x00000fff, iomemtype);
return s;
}
void pxa25x_timer_init(target_phys_addr_t base,
qemu_irq *irqs, CPUState *cpustate)
{
pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs, cpustate);
s->freq = PXA25X_FREQ;
s->tm4 = 0;
}
void pxa27x_timer_init(target_phys_addr_t base,
qemu_irq *irqs, qemu_irq irq4, CPUState *cpustate)
{
pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs, cpustate);
int i;
s->freq = PXA27X_FREQ;
s->tm4 = (struct pxa2xx_timer4_s *) qemu_mallocz(8 *
sizeof(struct pxa2xx_timer4_s));
for (i = 0; i < 8; i ++) {
s->tm4[i].value = 0;
s->tm4[i].irq = irq4;
s->tm4[i].info = s;
s->tm4[i].num = i + 4;
s->tm4[i].level = 0;
s->tm4[i].freq = 0;
s->tm4[i].control = 0x0;
s->tm4[i].qtimer = qemu_new_timer(vm_clock,
pxa2xx_timer_tick4, &s->tm4[i]);
}
}

21
vl.c
View file

@ -188,6 +188,7 @@ const char *vnc_display;
int acpi_enabled = 1;
int fd_bootchk = 1;
int no_reboot = 0;
int graphic_rotate = 0;
int daemonize = 0;
const char *option_rom[MAX_OPTION_ROMS];
int nb_option_roms;
@ -524,6 +525,7 @@ void kbd_mouse_event(int dx, int dy, int dz, int buttons_state)
{
QEMUPutMouseEvent *mouse_event;
void *mouse_event_opaque;
int width;
if (!qemu_put_mouse_event_current) {
return;
@ -535,7 +537,16 @@ void kbd_mouse_event(int dx, int dy, int dz, int buttons_state)
qemu_put_mouse_event_current->qemu_put_mouse_event_opaque;
if (mouse_event) {
mouse_event(mouse_event_opaque, dx, dy, dz, buttons_state);
if (graphic_rotate) {
if (qemu_put_mouse_event_current->qemu_put_mouse_event_absolute)
width = 0x7fff;
else
width = graphic_width;
mouse_event(mouse_event_opaque,
width - dy, dx, dz, buttons_state);
} else
mouse_event(mouse_event_opaque,
dx, dy, dz, buttons_state);
}
}
@ -6422,6 +6433,7 @@ void help(void)
"-m megs set virtual RAM size to megs MB [default=%d]\n"
"-smp n set the number of CPUs to 'n' [default=1]\n"
"-nographic disable graphical output and redirect serial I/Os to console\n"
"-portrait rotate graphical output 90 deg left (only PXA LCD)\n"
#ifndef _WIN32
"-k language use keyboard layout (for example \"fr\" for French)\n"
#endif
@ -6556,6 +6568,7 @@ enum {
#endif
QEMU_OPTION_m,
QEMU_OPTION_nographic,
QEMU_OPTION_portrait,
#ifdef HAS_AUDIO
QEMU_OPTION_audio_help,
QEMU_OPTION_soundhw,
@ -6636,6 +6649,7 @@ const QEMUOption qemu_options[] = {
#endif
{ "m", HAS_ARG, QEMU_OPTION_m },
{ "nographic", 0, QEMU_OPTION_nographic },
{ "portrait", 0, QEMU_OPTION_portrait },
{ "k", HAS_ARG, QEMU_OPTION_k },
#ifdef HAS_AUDIO
{ "audio-help", 0, QEMU_OPTION_audio_help },
@ -7167,6 +7181,9 @@ int main(int argc, char **argv)
pstrcpy(monitor_device, sizeof(monitor_device), "stdio");
nographic = 1;
break;
case QEMU_OPTION_portrait:
graphic_rotate = 1;
break;
case QEMU_OPTION_kernel:
kernel_filename = optarg;
break;
@ -7658,7 +7675,7 @@ int main(int argc, char **argv)
fprintf(stderr, "qemu: could not open SD card image %s\n",
sd_filename);
} else
qemu_key_check(bs, sd_filename);
qemu_key_check(sd_bdrv, sd_filename);
}
register_savevm("timer", 0, 2, timer_save, timer_load, NULL);

1
vl.h
View file

@ -158,6 +158,7 @@ extern int kqemu_allowed;
extern int win2k_install_hack;
extern int usb_enabled;
extern int smp_cpus;
extern int graphic_rotate;
extern int no_quit;
extern int semihosting_enabled;
extern int autostart;