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qapi: Drop inline nested structs in query-pci

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A future patch will be using a 'name':{dictionary} entry in the
QAPI schema to specify a default value for an optional argument
(see previous commit message for more details why); but existing
use of inline nested structs conflicts with that goal. This patch
fixes one of only two commands relying on nested types, by
breaking the nesting into an explicit type; it means that the
type is now boxed instead of unboxed in C code, but the QMP wire
format is unaffected by this change.

Prefer the safer g_new0() while making the conversion, and reduce
some long lines.

Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
This commit is contained in:
Eric Blake 2015-05-04 09:05:32 -06:00 committed by Markus Armbruster
parent 4752cdbbf3
commit 9fa02cd194
3 changed files with 98 additions and 60 deletions
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26
hmp.c
View file

@ -648,14 +648,14 @@ static void hmp_info_pci_device(Monitor *mon, const PciDeviceInfo *dev)
dev->slot, dev->function);
monitor_printf(mon, " ");
if (dev->class_info.has_desc) {
monitor_printf(mon, "%s", dev->class_info.desc);
if (dev->class_info->has_desc) {
monitor_printf(mon, "%s", dev->class_info->desc);
} else {
monitor_printf(mon, "Class %04" PRId64, dev->class_info.q_class);
monitor_printf(mon, "Class %04" PRId64, dev->class_info->q_class);
}
monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
dev->id.vendor, dev->id.device);
dev->id->vendor, dev->id->device);
if (dev->has_irq) {
monitor_printf(mon, " IRQ %" PRId64 ".\n", dev->irq);
@ -663,25 +663,25 @@ static void hmp_info_pci_device(Monitor *mon, const PciDeviceInfo *dev)
if (dev->has_pci_bridge) {
monitor_printf(mon, " BUS %" PRId64 ".\n",
dev->pci_bridge->bus.number);
dev->pci_bridge->bus->number);
monitor_printf(mon, " secondary bus %" PRId64 ".\n",
dev->pci_bridge->bus.secondary);
dev->pci_bridge->bus->secondary);
monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
dev->pci_bridge->bus.subordinate);
dev->pci_bridge->bus->subordinate);
monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
dev->pci_bridge->bus.io_range->base,
dev->pci_bridge->bus.io_range->limit);
dev->pci_bridge->bus->io_range->base,
dev->pci_bridge->bus->io_range->limit);
monitor_printf(mon,
" memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
dev->pci_bridge->bus.memory_range->base,
dev->pci_bridge->bus.memory_range->limit);
dev->pci_bridge->bus->memory_range->base,
dev->pci_bridge->bus->memory_range->limit);
monitor_printf(mon, " prefetchable memory range "
"[0x%08"PRIx64", 0x%08"PRIx64"]\n",
dev->pci_bridge->bus.prefetchable_range->base,
dev->pci_bridge->bus.prefetchable_range->limit);
dev->pci_bridge->bus->prefetchable_range->base,
dev->pci_bridge->bus->prefetchable_range->limit);
}
for (region = dev->regions; region; region = region->next) {

42
hw/pci/pci.c
View file

@ -1456,24 +1456,26 @@ static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
int bus_num)
{
PciBridgeInfo *info;
PciMemoryRange *range;
info = g_malloc0(sizeof(*info));
info = g_new0(PciBridgeInfo, 1);
info->bus.number = dev->config[PCI_PRIMARY_BUS];
info->bus.secondary = dev->config[PCI_SECONDARY_BUS];
info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS];
info->bus = g_new0(PciBusInfo, 1);
info->bus->number = dev->config[PCI_PRIMARY_BUS];
info->bus->secondary = dev->config[PCI_SECONDARY_BUS];
info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS];
info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range));
info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
range = info->bus->io_range = g_new0(PciMemoryRange, 1);
range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range));
info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
range = info->bus->memory_range = g_new0(PciMemoryRange, 1);
range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range));
info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1);
range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
if (dev->config[PCI_SECONDARY_BUS] != 0) {
PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
@ -1494,21 +1496,23 @@ static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
uint8_t type;
int class;
info = g_malloc0(sizeof(*info));
info = g_new0(PciDeviceInfo, 1);
info->bus = bus_num;
info->slot = PCI_SLOT(dev->devfn);
info->function = PCI_FUNC(dev->devfn);
info->class_info = g_new0(PciDeviceClass, 1);
class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
info->class_info.q_class = class;
info->class_info->q_class = class;
desc = get_class_desc(class);
if (desc->desc) {
info->class_info.has_desc = true;
info->class_info.desc = g_strdup(desc->desc);
info->class_info->has_desc = true;
info->class_info->desc = g_strdup(desc->desc);
}
info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID);
info->id = g_new0(PciDeviceId, 1);
info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID);
info->regions = qmp_query_pci_regions(dev);
info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");

90
qapi-schema.json
View file

@ -1040,37 +1040,76 @@
'data': {'bar': 'int', 'type': 'str', 'address': 'int', 'size': 'int',
'*prefetch': 'bool', '*mem_type_64': 'bool' } }
##
# @PciBusInfo:
#
# Information about a bus of a PCI Bridge device
#
# @number: primary bus interface number. This should be the number of the
# bus the device resides on.
#
# @secondary: secondary bus interface number. This is the number of the
# main bus for the bridge
#
# @subordinate: This is the highest number bus that resides below the
# bridge.
#
# @io_range: The PIO range for all devices on this bridge
#
# @memory_range: The MMIO range for all devices on this bridge
#
# @prefetchable_range: The range of prefetchable MMIO for all devices on
# this bridge
#
# Since: 2.4
##
{ 'struct': 'PciBusInfo',
'data': {'number': 'int', 'secondary': 'int', 'subordinate': 'int',
'io_range': 'PciMemoryRange',
'memory_range': 'PciMemoryRange',
'prefetchable_range': 'PciMemoryRange' } }
##
# @PciBridgeInfo:
#
# Information about a PCI Bridge device
#
# @bus.number: primary bus interface number. This should be the number of the
# bus the device resides on.
#
# @bus.secondary: secondary bus interface number. This is the number of the
# main bus for the bridge
#
# @bus.subordinate: This is the highest number bus that resides below the
# bridge.
#
# @bus.io_range: The PIO range for all devices on this bridge
#
# @bus.memory_range: The MMIO range for all devices on this bridge
#
# @bus.prefetchable_range: The range of prefetchable MMIO for all devices on
# this bridge
# @bus: information about the bus the device resides on
#
# @devices: a list of @PciDeviceInfo for each device on this bridge
#
# Since: 0.14.0
##
{ 'struct': 'PciBridgeInfo',
'data': {'bus': { 'number': 'int', 'secondary': 'int', 'subordinate': 'int',
'io_range': 'PciMemoryRange',
'memory_range': 'PciMemoryRange',
'prefetchable_range': 'PciMemoryRange' },
'*devices': ['PciDeviceInfo']} }
'data': {'bus': 'PciBusInfo', '*devices': ['PciDeviceInfo']} }
##
# @PciDeviceClass:
#
# Information about the Class of a PCI device
#
# @desc: #optional a string description of the device's class
#
# @class: the class code of the device
#
# Since: 2.4
##
{ 'struct': 'PciDeviceClass',
'data': {'*desc': 'str', 'class': 'int'} }
##
# @PciDeviceId:
#
# Information about the Id of a PCI device
#
# @device: the PCI device id
#
# @vendor: the PCI vendor id
#
# Since: 2.4
##
{ 'struct': 'PciDeviceId',
'data': {'device': 'int', 'vendor': 'int'} }
##
# @PciDeviceInfo:
@ -1083,13 +1122,9 @@
#
# @function: the function of the slot used by the device
#
# @class_info.desc: #optional a string description of the device's class
# @class_info: the class of the device
#
# @class_info.class: the class code of the device
#
# @id.device: the PCI device id
#
# @id.vendor: the PCI vendor id
# @id: the PCI device id
#
# @irq: #optional if an IRQ is assigned to the device, the IRQ number
#
@ -1106,8 +1141,7 @@
##
{ 'struct': 'PciDeviceInfo',
'data': {'bus': 'int', 'slot': 'int', 'function': 'int',
'class_info': {'*desc': 'str', 'class': 'int'},
'id': {'device': 'int', 'vendor': 'int'},
'class_info': 'PciDeviceClass', 'id': 'PciDeviceId',
'*irq': 'int', 'qdev_id': 'str', '*pci_bridge': 'PciBridgeInfo',
'regions': ['PciMemoryRegion']} }