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https://gitlab.com/qemu-project/qemu
synced 2024-09-06 18:05:37 +00:00
target/i386: Reorg GET_HPHYS
Replace with PTE_HPHYS for the page table walk, and a direct call to mmu_translate for the final stage2 translation. Hoist the check for HF2_NPT_MASK out to get_physical_address, which avoids the recursive call when stage2 is disabled. We can now return all the way out to x86_cpu_tlb_fill before raising an exception, which means probe works. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221002172956.265735-5-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
parent
3563362ddf
commit
9bbcf37219
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@ -37,18 +37,43 @@ typedef struct TranslateResult {
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int page_size;
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int page_size;
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} TranslateResult;
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} TranslateResult;
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typedef enum TranslateFaultStage2 {
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S2_NONE,
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S2_GPA,
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S2_GPT,
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} TranslateFaultStage2;
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typedef struct TranslateFault {
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typedef struct TranslateFault {
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int exception_index;
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int exception_index;
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int error_code;
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int error_code;
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target_ulong cr2;
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target_ulong cr2;
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TranslateFaultStage2 stage2;
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} TranslateFault;
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} TranslateFault;
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#define GET_HPHYS(cs, gpa, access_type, prot) \
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#define PTE_HPHYS(ADDR) \
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(in->use_stage2 ? get_hphys(cs, gpa, access_type, prot) : gpa)
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do { \
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if (in->use_stage2) { \
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nested_in.addr = (ADDR); \
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if (!mmu_translate(env, &nested_in, out, err)) { \
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err->stage2 = S2_GPT; \
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return false; \
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} \
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(ADDR) = out->paddr; \
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} \
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} while (0)
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static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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TranslateResult *out, TranslateFault *err)
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TranslateResult *out, TranslateFault *err)
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{
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{
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TranslateParams nested_in = {
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/* Use store for page table entries, to allow A/D flag updates. */
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.access_type = MMU_DATA_STORE,
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.cr3 = env->nested_cr3,
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.pg_mode = env->nested_pg_mode,
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.mmu_idx = MMU_USER_IDX,
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.use_stage2 = false,
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};
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CPUState *cs = env_cpu(env);
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CPUState *cs = env_cpu(env);
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X86CPU *cpu = env_archcpu(env);
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X86CPU *cpu = env_archcpu(env);
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const int32_t a20_mask = x86_get_a20_mask(env);
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const int32_t a20_mask = x86_get_a20_mask(env);
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@ -79,7 +104,7 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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if (la57) {
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if (la57) {
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pml5e_addr = ((in->cr3 & ~0xfff) +
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pml5e_addr = ((in->cr3 & ~0xfff) +
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(((addr >> 48) & 0x1ff) << 3)) & a20_mask;
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(((addr >> 48) & 0x1ff) << 3)) & a20_mask;
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pml5e_addr = GET_HPHYS(cs, pml5e_addr, MMU_DATA_STORE, NULL);
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PTE_HPHYS(pml5e_addr);
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pml5e = x86_ldq_phys(cs, pml5e_addr);
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pml5e = x86_ldq_phys(cs, pml5e_addr);
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if (!(pml5e & PG_PRESENT_MASK)) {
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if (!(pml5e & PG_PRESENT_MASK)) {
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goto do_fault;
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goto do_fault;
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@ -99,7 +124,7 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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pml4e_addr = ((pml5e & PG_ADDRESS_MASK) +
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pml4e_addr = ((pml5e & PG_ADDRESS_MASK) +
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(((addr >> 39) & 0x1ff) << 3)) & a20_mask;
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(((addr >> 39) & 0x1ff) << 3)) & a20_mask;
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pml4e_addr = GET_HPHYS(cs, pml4e_addr, MMU_DATA_STORE, NULL);
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PTE_HPHYS(pml4e_addr);
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pml4e = x86_ldq_phys(cs, pml4e_addr);
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pml4e = x86_ldq_phys(cs, pml4e_addr);
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if (!(pml4e & PG_PRESENT_MASK)) {
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if (!(pml4e & PG_PRESENT_MASK)) {
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goto do_fault;
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goto do_fault;
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@ -114,7 +139,7 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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ptep &= pml4e ^ PG_NX_MASK;
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ptep &= pml4e ^ PG_NX_MASK;
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pdpe_addr = ((pml4e & PG_ADDRESS_MASK) + (((addr >> 30) & 0x1ff) << 3)) &
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pdpe_addr = ((pml4e & PG_ADDRESS_MASK) + (((addr >> 30) & 0x1ff) << 3)) &
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a20_mask;
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a20_mask;
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pdpe_addr = GET_HPHYS(cs, pdpe_addr, MMU_DATA_STORE, NULL);
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PTE_HPHYS(pdpe_addr);
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pdpe = x86_ldq_phys(cs, pdpe_addr);
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pdpe = x86_ldq_phys(cs, pdpe_addr);
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if (!(pdpe & PG_PRESENT_MASK)) {
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if (!(pdpe & PG_PRESENT_MASK)) {
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goto do_fault;
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goto do_fault;
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@ -140,7 +165,7 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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/* XXX: load them when cr3 is loaded ? */
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/* XXX: load them when cr3 is loaded ? */
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pdpe_addr = ((in->cr3 & ~0x1f) + ((addr >> 27) & 0x18)) &
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pdpe_addr = ((in->cr3 & ~0x1f) + ((addr >> 27) & 0x18)) &
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a20_mask;
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a20_mask;
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pdpe_addr = GET_HPHYS(cs, pdpe_addr, MMU_DATA_STORE, NULL);
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PTE_HPHYS(pdpe_addr);
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pdpe = x86_ldq_phys(cs, pdpe_addr);
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pdpe = x86_ldq_phys(cs, pdpe_addr);
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if (!(pdpe & PG_PRESENT_MASK)) {
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if (!(pdpe & PG_PRESENT_MASK)) {
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goto do_fault;
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goto do_fault;
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@ -154,7 +179,7 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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pde_addr = ((pdpe & PG_ADDRESS_MASK) + (((addr >> 21) & 0x1ff) << 3)) &
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pde_addr = ((pdpe & PG_ADDRESS_MASK) + (((addr >> 21) & 0x1ff) << 3)) &
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a20_mask;
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a20_mask;
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pde_addr = GET_HPHYS(cs, pde_addr, MMU_DATA_STORE, NULL);
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PTE_HPHYS(pde_addr);
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pde = x86_ldq_phys(cs, pde_addr);
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pde = x86_ldq_phys(cs, pde_addr);
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if (!(pde & PG_PRESENT_MASK)) {
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if (!(pde & PG_PRESENT_MASK)) {
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goto do_fault;
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goto do_fault;
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@ -177,7 +202,7 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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}
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}
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pte_addr = ((pde & PG_ADDRESS_MASK) + (((addr >> 12) & 0x1ff) << 3)) &
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pte_addr = ((pde & PG_ADDRESS_MASK) + (((addr >> 12) & 0x1ff) << 3)) &
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a20_mask;
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a20_mask;
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pte_addr = GET_HPHYS(cs, pte_addr, MMU_DATA_STORE, NULL);
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PTE_HPHYS(pte_addr);
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pte = x86_ldq_phys(cs, pte_addr);
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pte = x86_ldq_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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goto do_fault;
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@ -194,7 +219,7 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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/* page directory entry */
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/* page directory entry */
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pde_addr = ((in->cr3 & ~0xfff) + ((addr >> 20) & 0xffc)) &
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pde_addr = ((in->cr3 & ~0xfff) + ((addr >> 20) & 0xffc)) &
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a20_mask;
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a20_mask;
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pde_addr = GET_HPHYS(cs, pde_addr, MMU_DATA_STORE, NULL);
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PTE_HPHYS(pde_addr);
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pde = x86_ldl_phys(cs, pde_addr);
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pde = x86_ldl_phys(cs, pde_addr);
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if (!(pde & PG_PRESENT_MASK)) {
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if (!(pde & PG_PRESENT_MASK)) {
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goto do_fault;
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goto do_fault;
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@ -222,7 +247,7 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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/* page directory entry */
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/* page directory entry */
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pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) &
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pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) &
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a20_mask;
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a20_mask;
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pte_addr = GET_HPHYS(cs, pte_addr, MMU_DATA_STORE, NULL);
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PTE_HPHYS(pte_addr);
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pte = x86_ldl_phys(cs, pte_addr);
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pte = x86_ldl_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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goto do_fault;
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@ -303,13 +328,31 @@ do_check_protect_pse36:
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assert(access_type != MMU_DATA_STORE);
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assert(access_type != MMU_DATA_STORE);
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prot &= ~PAGE_WRITE;
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prot &= ~PAGE_WRITE;
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}
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}
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out->prot = prot;
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out->page_size = page_size;
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/* align to page_size */
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/* align to page_size */
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out->paddr = (pte & a20_mask & PG_ADDRESS_MASK & ~(page_size - 1))
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out->paddr = (pte & a20_mask & PG_ADDRESS_MASK & ~(page_size - 1))
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| (addr & (page_size - 1));
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out->paddr = GET_HPHYS(cs, out->paddr, access_type, &out->prot);
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if (in->use_stage2) {
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nested_in.addr = out->paddr;
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nested_in.access_type = access_type;
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if (!mmu_translate(env, &nested_in, out, err)) {
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err->stage2 = S2_GPA;
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return false;
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}
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/* Merge stage1 & stage2 protection bits. */
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prot &= out->prot;
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/* Re-verify resulting protection. */
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if ((prot & (1 << access_type)) == 0) {
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goto do_fault_protect;
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}
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}
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out->prot = prot;
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out->page_size = page_size;
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return true;
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return true;
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int error_code;
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int error_code;
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@ -344,13 +387,36 @@ do_check_protect_pse36:
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err->exception_index = EXCP0E_PAGE;
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err->exception_index = EXCP0E_PAGE;
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err->error_code = error_code;
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err->error_code = error_code;
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err->cr2 = addr;
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err->cr2 = addr;
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err->stage2 = S2_NONE;
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return false;
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return false;
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}
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}
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static G_NORETURN void raise_stage2(CPUX86State *env, TranslateFault *err,
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uintptr_t retaddr)
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{
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uint64_t exit_info_1 = err->error_code;
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switch (err->stage2) {
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case S2_GPT:
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exit_info_1 |= SVM_NPTEXIT_GPT;
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break;
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case S2_GPA:
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exit_info_1 |= SVM_NPTEXIT_GPA;
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break;
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default:
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g_assert_not_reached();
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}
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x86_stq_phys(env_cpu(env),
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env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
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err->cr2);
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cpu_vmexit(env, SVM_EXIT_NPF, exit_info_1, retaddr);
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}
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hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
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hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
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int *prot)
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int *prot)
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{
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{
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CPUX86State *env = &X86_CPU(cs)->env;
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CPUX86State *env = cs->env_ptr;
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if (likely(!(env->hflags2 & HF2_NPT_MASK))) {
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if (likely(!(env->hflags2 & HF2_NPT_MASK))) {
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return gphys;
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return gphys;
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@ -365,20 +431,16 @@ hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
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};
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};
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TranslateResult out;
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TranslateResult out;
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TranslateFault err;
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TranslateFault err;
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uint64_t exit_info_1;
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if (mmu_translate(env, &in, &out, &err)) {
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if (!mmu_translate(env, &in, &out, &err)) {
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if (prot) {
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err.stage2 = prot ? SVM_NPTEXIT_GPA : SVM_NPTEXIT_GPT;
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*prot &= out.prot;
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raise_stage2(env, &err, env->retaddr);
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}
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return out.paddr;
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}
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}
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x86_stq_phys(cs, env->vm_vmcb +
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if (prot) {
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offsetof(struct vmcb, control.exit_info_2), gphys);
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*prot &= out.prot;
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exit_info_1 = err.error_code
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}
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return out.paddr;
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cpu_vmexit(env, SVM_EXIT_NPF, exit_info_1, env->retaddr);
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}
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}
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}
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}
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@ -405,7 +467,7 @@ static bool get_physical_address(CPUX86State *env, vaddr addr,
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.pg_mode = get_pg_mode(env),
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.pg_mode = get_pg_mode(env),
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.mmu_idx = mmu_idx,
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.mmu_idx = mmu_idx,
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.access_type = access_type,
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.access_type = access_type,
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.use_stage2 = true
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.use_stage2 = env->hflags2 & HF2_NPT_MASK,
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};
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};
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if (in.pg_mode & PG_MODE_LMA) {
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if (in.pg_mode & PG_MODE_LMA) {
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@ -444,8 +506,13 @@ bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
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return true;
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return true;
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}
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}
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/* FIXME: On error in get_hphys we have already jumped out. */
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if (probe) {
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g_assert(!probe);
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return false;
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}
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if (err.stage2 != S2_NONE) {
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raise_stage2(env, &err, retaddr);
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}
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if (env->intercept_exceptions & (1 << err.exception_index)) {
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if (env->intercept_exceptions & (1 << err.exception_index)) {
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/* cr2 is not modified in case of exceptions */
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/* cr2 is not modified in case of exceptions */
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