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sh_serial: convert to memory API
Signed-off-by: Benoit Canet <benoit.canet@gmail.com> Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
parent
b279e5efc0
commit
9a9d0b816b
3
hw/sh.h
3
hw/sh.h
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@ -39,7 +39,8 @@ void tmu012_init(struct MemoryRegion *sysmem, target_phys_addr_t base,
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/* sh_serial.c */
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#define SH_SERIAL_FEAT_SCIF (1 << 0)
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void sh_serial_init (target_phys_addr_t base, int feat,
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void sh_serial_init(MemoryRegion *sysmem,
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target_phys_addr_t base, int feat,
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uint32_t freq, CharDriverState *chr,
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qemu_irq eri_source,
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qemu_irq rxi_source,
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28
hw/sh7750.c
28
hw/sh7750.c
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@ -766,19 +766,21 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
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cpu->intc_handle = &s->intc;
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sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0],
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s->intc.irqs[SCI1_ERI],
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s->intc.irqs[SCI1_RXI],
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s->intc.irqs[SCI1_TXI],
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s->intc.irqs[SCI1_TEI],
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NULL);
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sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
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s->periph_freq, serial_hds[1],
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s->intc.irqs[SCIF_ERI],
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s->intc.irqs[SCIF_RXI],
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s->intc.irqs[SCIF_TXI],
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NULL,
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s->intc.irqs[SCIF_BRI]);
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sh_serial_init(sysmem, 0x1fe00000,
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0, s->periph_freq, serial_hds[0],
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s->intc.irqs[SCI1_ERI],
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s->intc.irqs[SCI1_RXI],
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s->intc.irqs[SCI1_TXI],
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s->intc.irqs[SCI1_TEI],
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NULL);
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sh_serial_init(sysmem, 0x1fe80000,
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SH_SERIAL_FEAT_SCIF,
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s->periph_freq, serial_hds[1],
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s->intc.irqs[SCIF_ERI],
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s->intc.irqs[SCIF_RXI],
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s->intc.irqs[SCIF_TXI],
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NULL,
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s->intc.irqs[SCIF_BRI]);
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tmu012_init(sysmem, 0x1fd80000,
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TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
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@ -27,6 +27,7 @@
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#include "hw.h"
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#include "sh.h"
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#include "qemu-char.h"
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#include "exec-memory.h"
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//#define DEBUG_SERIAL
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@ -39,6 +40,9 @@
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#define SH_RX_FIFO_LENGTH (16)
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typedef struct {
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MemoryRegion iomem;
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MemoryRegion iomem_p4;
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MemoryRegion iomem_a7;
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uint8_t smr;
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uint8_t brr;
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uint8_t scr;
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@ -74,7 +78,8 @@ static void sh_serial_clear_fifo(sh_serial_state * s)
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s->rx_tail = 0;
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}
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static void sh_serial_write(void *opaque, uint32_t offs, uint32_t val)
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static void sh_serial_write(void *opaque, target_phys_addr_t offs,
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uint64_t val, unsigned size)
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{
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sh_serial_state *s = opaque;
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unsigned char ch;
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@ -185,7 +190,8 @@ static void sh_serial_write(void *opaque, uint32_t offs, uint32_t val)
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abort();
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}
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static uint32_t sh_serial_read(void *opaque, uint32_t offs)
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static uint64_t sh_serial_read(void *opaque, target_phys_addr_t offs,
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unsigned size)
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{
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sh_serial_state *s = opaque;
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uint32_t ret = ~0;
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@ -338,28 +344,22 @@ static void sh_serial_event(void *opaque, int event)
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sh_serial_receive_break(s);
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}
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static CPUReadMemoryFunc * const sh_serial_readfn[] = {
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&sh_serial_read,
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&sh_serial_read,
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&sh_serial_read,
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static const MemoryRegionOps sh_serial_ops = {
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.read = sh_serial_read,
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.write = sh_serial_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static CPUWriteMemoryFunc * const sh_serial_writefn[] = {
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&sh_serial_write,
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&sh_serial_write,
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&sh_serial_write,
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};
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void sh_serial_init (target_phys_addr_t base, int feat,
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uint32_t freq, CharDriverState *chr,
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qemu_irq eri_source,
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qemu_irq rxi_source,
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qemu_irq txi_source,
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qemu_irq tei_source,
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qemu_irq bri_source)
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void sh_serial_init(MemoryRegion *sysmem,
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target_phys_addr_t base, int feat,
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uint32_t freq, CharDriverState *chr,
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qemu_irq eri_source,
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qemu_irq rxi_source,
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qemu_irq txi_source,
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qemu_irq tei_source,
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qemu_irq bri_source)
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{
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sh_serial_state *s;
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int s_io_memory;
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s = g_malloc0(sizeof(sh_serial_state));
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@ -381,11 +381,16 @@ void sh_serial_init (target_phys_addr_t base, int feat,
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sh_serial_clear_fifo(s);
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s_io_memory = cpu_register_io_memory(sh_serial_readfn,
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sh_serial_writefn, s,
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DEVICE_NATIVE_ENDIAN);
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cpu_register_physical_memory(P4ADDR(base), 0x28, s_io_memory);
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cpu_register_physical_memory(A7ADDR(base), 0x28, s_io_memory);
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memory_region_init_io(&s->iomem, &sh_serial_ops, s,
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"serial", 0x100000000ULL);
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memory_region_init_alias(&s->iomem_p4, "serial-p4", &s->iomem,
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0, 0x28);
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memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
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memory_region_init_alias(&s->iomem_a7, "serial-a7", &s->iomem,
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0, 0x28);
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memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
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s->chr = chr;
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