mirror of
https://gitlab.com/qemu-project/qemu
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OMAP2 EAC module.
Not yet hooked up to any CODEC. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4886 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog
parent
dcf414d638
commit
99570a40eb
3 changed files with 556 additions and 4 deletions
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@ -57,7 +57,7 @@ struct n800_s {
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#define N800_MMC2_WP_GPIO 8
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#define N800_UNKNOWN_GPIO0 9 /* out */
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#define N810_MMC2_VIOSD_GPIO 9
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#define N800_UNKNOWN_GPIO1 10 /* out */
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#define N810_HEADSET_AMP_GPIO 10
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#define N800_CAM_TURN_GPIO 12
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#define N810_GPS_RESET_GPIO 12
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#define N800_BLIZZARD_POWERDOWN_GPIO 15
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@ -82,7 +82,7 @@ struct n800_s {
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#define N8X0_MMC_CS_GPIO 96
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#define N8X0_WLAN_PWR_GPIO 97
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#define N8X0_BT_HOST_WKUP_GPIO 98
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#define N800_UNKNOWN_GPIO3 101 /* out */
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#define N810_SPEAKER_AMP_GPIO 101
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#define N810_KB_LOCK_GPIO 102
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#define N800_TSC_TS_GPIO 103
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#define N810_TSC_TS_GPIO 106
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@ -96,6 +96,7 @@ struct n800_s {
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#define N800_UNKNOWN_GPIO4 112 /* out */
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#define N810_SLEEPX_LED_GPIO 112
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#define N800_TSC_RESET_GPIO 118 /* ? */
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#define N810_AIC33_RESET_GPIO 118
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#define N800_TSC_UNKNOWN_GPIO 119 /* out */
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#define N8X0_TMP105_GPIO 125
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@ -738,6 +738,10 @@ struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk);
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void omap_tap_init(struct omap_target_agent_s *ta,
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struct omap_mpu_state_s *mpu);
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struct omap_eac_s;
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struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
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qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
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/* omap_lcdc.c */
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struct omap_lcd_panel_s;
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void omap_lcdc_reset(struct omap_lcd_panel_s *s);
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@ -957,6 +961,8 @@ struct omap_mpu_state_s {
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struct omap_mcspi_s *mcspi[2];
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struct omap_dss_s *dss;
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struct omap_eac_s *eac;
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};
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/* omap1.c */
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549
hw/omap2.c
549
hw/omap2.c
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@ -26,6 +26,7 @@
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#include "qemu-timer.h"
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#include "qemu-char.h"
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#include "flash.h"
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#include "audio/audio.h"
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/* GP timers */
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struct omap_gp_timer_s {
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@ -1420,6 +1421,541 @@ void omap_mcspi_attach(struct omap_mcspi_s *s,
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s->ch[chipselect].opaque = opaque;
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}
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/* Enhanced Audio Controller (CODEC only) */
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struct omap_eac_s {
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target_phys_addr_t base;
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qemu_irq irq;
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uint16_t sysconfig;
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uint8_t config[4];
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uint8_t control;
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uint8_t address;
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uint16_t data;
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uint8_t vtol;
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uint8_t vtsl;
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uint16_t mixer;
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uint16_t gain[4];
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uint8_t att;
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uint16_t max[7];
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struct {
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qemu_irq txdrq;
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qemu_irq rxdrq;
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uint32_t (*txrx)(void *opaque, uint32_t, int);
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void *opaque;
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#define EAC_BUF_LEN 1024
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uint32_t rxbuf[EAC_BUF_LEN];
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int rxlen;
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int rxavail;
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uint32_t txbuf[EAC_BUF_LEN];
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int txlen;
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int txavail;
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int enable;
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int rate;
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uint16_t config[4];
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/* These need to be moved to the actual codec */
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QEMUSoundCard card;
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SWVoiceIn *in_voice;
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SWVoiceOut *out_voice;
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int hw_enable;
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} codec;
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struct {
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uint8_t control;
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uint16_t config;
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} modem, bt;
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};
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static inline void omap_eac_interrupt_update(struct omap_eac_s *s)
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{
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qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */
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}
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static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s)
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{
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qemu_set_irq(s->codec.rxdrq, s->codec.rxavail + s->codec.rxlen &&
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((s->codec.config[1] >> 12) & 1)); /* DMAREN */
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}
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static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s)
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{
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qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail &&
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((s->codec.config[1] >> 11) & 1)); /* DMAWEN */
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}
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static inline void omap_eac_in_refill(struct omap_eac_s *s)
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{
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int left, start = 0;
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s->codec.rxlen = MIN(s->codec.rxavail, EAC_BUF_LEN);
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s->codec.rxavail -= s->codec.rxlen;
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for (left = s->codec.rxlen << 2; left; start = (EAC_BUF_LEN << 2) - left)
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left -= AUD_read(s->codec.in_voice,
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(uint8_t *) s->codec.rxbuf + start, left);
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}
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static inline void omap_eac_out_empty(struct omap_eac_s *s)
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{
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int left, start = 0;
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for (left = s->codec.txlen << 2; left; start = (s->codec.txlen << 2) - left)
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left -= AUD_write(s->codec.out_voice,
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(uint8_t *) s->codec.txbuf + start, left);
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s->codec.txavail -= s->codec.txlen;
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s->codec.txlen = 0;
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}
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static void omap_eac_in_cb(void *opaque, int avail_b)
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{
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struct omap_eac_s *s = (struct omap_eac_s *) opaque;
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s->codec.rxavail = avail_b >> 2;
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omap_eac_in_dmarequest_update(s);
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/* TODO: possibly discard current buffer if overrun */
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}
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static void omap_eac_out_cb(void *opaque, int free_b)
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{
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struct omap_eac_s *s = (struct omap_eac_s *) opaque;
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s->codec.txavail = free_b >> 2;
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if (s->codec.txlen > s->codec.txavail)
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s->codec.txlen = s->codec.txavail;
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omap_eac_out_empty(s);
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omap_eac_out_dmarequest_update(s);
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}
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static void omap_eac_enable_update(struct omap_eac_s *s)
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{
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s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */
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(s->codec.config[1] & 2) && /* AUDEN */
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s->codec.hw_enable;
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}
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static const int omap_eac_fsint[4] = {
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8000,
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11025,
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22050,
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44100,
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};
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static const int omap_eac_fsint2[8] = {
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8000,
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11025,
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22050,
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44100,
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48000,
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0, 0, 0,
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};
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static const int omap_eac_fsint3[16] = {
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8000,
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11025,
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16000,
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22050,
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24000,
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32000,
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44100,
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48000,
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0, 0, 0, 0, 0, 0, 0, 0,
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};
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static void omap_eac_rate_update(struct omap_eac_s *s)
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{
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int fsint[3];
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fsint[2] = (s->codec.config[3] >> 9) & 0xf;
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fsint[1] = (s->codec.config[2] >> 0) & 0x7;
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fsint[0] = (s->codec.config[0] >> 6) & 0x3;
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if (fsint[2] < 0xf)
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s->codec.rate = omap_eac_fsint3[fsint[2]];
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else if (fsint[1] < 0x7)
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s->codec.rate = omap_eac_fsint2[fsint[1]];
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else
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s->codec.rate = omap_eac_fsint[fsint[0]];
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}
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static void omap_eac_volume_update(struct omap_eac_s *s)
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{
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/* TODO */
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}
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static void omap_eac_format_update(struct omap_eac_s *s)
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{
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audsettings_t fmt;
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omap_eac_out_empty(s);
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if (s->codec.in_voice) {
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AUD_set_active_in(s->codec.in_voice, 0);
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AUD_close_in(&s->codec.card, s->codec.in_voice);
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s->codec.in_voice = 0;
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}
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if (s->codec.out_voice) {
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AUD_set_active_out(s->codec.out_voice, 0);
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AUD_close_out(&s->codec.card, s->codec.out_voice);
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s->codec.out_voice = 0;
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}
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omap_eac_enable_update(s);
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if (!s->codec.enable)
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return;
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omap_eac_rate_update(s);
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fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */
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fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */
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fmt.freq = s->codec.rate;
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/* TODO: signedness possibly depends on the CODEC hardware - or
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* does I2S specify it? */
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/* All register writes are 16 bits so we we store 16-bit samples
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* in the buffers regardless of AGCFR[B8_16] value. */
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fmt.fmt = AUD_FMT_U16;
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s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice,
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"eac.codec.in", s, omap_eac_in_cb, &fmt);
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s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice,
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"eac.codec.out", s, omap_eac_out_cb, &fmt);
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omap_eac_volume_update(s);
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AUD_set_active_in(s->codec.in_voice, 1);
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AUD_set_active_out(s->codec.out_voice, 1);
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}
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static void omap_eac_reset(struct omap_eac_s *s)
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{
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s->sysconfig = 0;
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s->config[0] = 0x0c;
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s->config[1] = 0x09;
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s->config[2] = 0xab;
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s->config[3] = 0x03;
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s->control = 0x00;
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s->address = 0x00;
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s->data = 0x0000;
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s->vtol = 0x00;
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s->vtsl = 0x00;
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s->mixer = 0x0000;
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s->gain[0] = 0xe7e7;
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s->gain[1] = 0x6767;
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s->gain[2] = 0x6767;
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s->gain[3] = 0x6767;
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s->att = 0xce;
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s->max[0] = 0;
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s->max[1] = 0;
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s->max[2] = 0;
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s->max[3] = 0;
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s->max[4] = 0;
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s->max[5] = 0;
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s->max[6] = 0;
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s->modem.control = 0x00;
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s->modem.config = 0x0000;
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s->bt.control = 0x00;
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s->bt.config = 0x0000;
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s->codec.config[0] = 0x0649;
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s->codec.config[1] = 0x0000;
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s->codec.config[2] = 0x0007;
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s->codec.config[3] = 0x1ffc;
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s->codec.rxlen = 0;
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s->codec.txlen = 0;
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s->codec.rxavail = 0;
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s->codec.txavail = 0;
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omap_eac_format_update(s);
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omap_eac_interrupt_update(s);
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}
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static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr)
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{
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struct omap_eac_s *s = (struct omap_eac_s *) opaque;
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int offset = addr - s->base;
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switch (offset) {
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case 0x000: /* CPCFR1 */
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return s->config[0];
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case 0x004: /* CPCFR2 */
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return s->config[1];
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case 0x008: /* CPCFR3 */
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return s->config[2];
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case 0x00c: /* CPCFR4 */
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return s->config[3];
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case 0x010: /* CPTCTL */
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return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) |
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((s->codec.txlen < s->codec.txavail) << 5);
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case 0x014: /* CPTTADR */
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return s->address;
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case 0x018: /* CPTDATL */
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return s->data & 0xff;
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case 0x01c: /* CPTDATH */
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return s->data >> 8;
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case 0x020: /* CPTVSLL */
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return s->vtol;
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case 0x024: /* CPTVSLH */
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return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */
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case 0x040: /* MPCTR */
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return s->modem.control;
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case 0x044: /* MPMCCFR */
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return s->modem.config;
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case 0x060: /* BPCTR */
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return s->bt.control;
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case 0x064: /* BPMCCFR */
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return s->bt.config;
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case 0x080: /* AMSCFR */
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return s->mixer;
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case 0x084: /* AMVCTR */
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return s->gain[0];
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case 0x088: /* AM1VCTR */
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return s->gain[1];
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case 0x08c: /* AM2VCTR */
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return s->gain[2];
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case 0x090: /* AM3VCTR */
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return s->gain[3];
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case 0x094: /* ASTCTR */
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return s->att;
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case 0x098: /* APD1LCR */
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return s->max[0];
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case 0x09c: /* APD1RCR */
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return s->max[1];
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case 0x0a0: /* APD2LCR */
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return s->max[2];
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case 0x0a4: /* APD2RCR */
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return s->max[3];
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case 0x0a8: /* APD3LCR */
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return s->max[4];
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case 0x0ac: /* APD3RCR */
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return s->max[5];
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case 0x0b0: /* APD4R */
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return s->max[6];
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case 0x0b4: /* ADWR */
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/* This should be write-only? Docs list it as read-only. */
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return 0x0000;
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case 0x0b8: /* ADRDR */
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if (likely(s->codec.rxlen > 1))
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return s->codec.rxbuf[EAC_BUF_LEN - s->codec.rxlen --];
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else if (s->codec.rxlen) {
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if (s->codec.rxavail)
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omap_eac_in_refill(s);
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else {
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s->codec.rxlen = 0;
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omap_eac_in_dmarequest_update(s);
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}
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return s->codec.rxbuf[EAC_BUF_LEN - 1];
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}
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return 0x0000;
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case 0x0bc: /* AGCFR */
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return s->codec.config[0];
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case 0x0c0: /* AGCTR */
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return s->codec.config[1] | ((s->codec.config[1] & 2) << 14);
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case 0x0c4: /* AGCFR2 */
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return s->codec.config[2];
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case 0x0c8: /* AGCFR3 */
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return s->codec.config[3];
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case 0x0cc: /* MBPDMACTR */
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case 0x0d0: /* MPDDMARR */
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case 0x0d8: /* MPUDMARR */
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case 0x0e4: /* BPDDMARR */
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case 0x0ec: /* BPUDMARR */
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return 0x0000;
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case 0x100: /* VERSION_NUMBER */
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return 0x0010;
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case 0x104: /* SYSCONFIG */
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return s->sysconfig;
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case 0x108: /* SYSSTATUS */
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return 1 | 0xe; /* RESETDONE | stuff */
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}
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OMAP_BAD_REG(addr);
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return 0;
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}
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static void omap_eac_write(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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struct omap_eac_s *s = (struct omap_eac_s *) opaque;
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int offset = addr - s->base;
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switch (offset) {
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case 0x098: /* APD1LCR */
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case 0x09c: /* APD1RCR */
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case 0x0a0: /* APD2LCR */
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case 0x0a4: /* APD2RCR */
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case 0x0a8: /* APD3LCR */
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case 0x0ac: /* APD3RCR */
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case 0x0b0: /* APD4R */
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||||
case 0x0b8: /* ADRDR */
|
||||
case 0x0d0: /* MPDDMARR */
|
||||
case 0x0d8: /* MPUDMARR */
|
||||
case 0x0e4: /* BPDDMARR */
|
||||
case 0x0ec: /* BPUDMARR */
|
||||
case 0x100: /* VERSION_NUMBER */
|
||||
case 0x108: /* SYSSTATUS */
|
||||
OMAP_RO_REG(addr);
|
||||
return;
|
||||
|
||||
case 0x000: /* CPCFR1 */
|
||||
s->config[0] = value & 0xff;
|
||||
omap_eac_format_update(s);
|
||||
break;
|
||||
case 0x004: /* CPCFR2 */
|
||||
s->config[1] = value & 0xff;
|
||||
omap_eac_format_update(s);
|
||||
break;
|
||||
case 0x008: /* CPCFR3 */
|
||||
s->config[2] = value & 0xff;
|
||||
omap_eac_format_update(s);
|
||||
break;
|
||||
case 0x00c: /* CPCFR4 */
|
||||
s->config[3] = value & 0xff;
|
||||
omap_eac_format_update(s);
|
||||
break;
|
||||
|
||||
case 0x010: /* CPTCTL */
|
||||
/* Assuming TXF and TXE bits are read-only... */
|
||||
s->control = value & 0x5f;
|
||||
omap_eac_interrupt_update(s);
|
||||
break;
|
||||
|
||||
case 0x014: /* CPTTADR */
|
||||
s->address = value & 0xff;
|
||||
break;
|
||||
case 0x018: /* CPTDATL */
|
||||
s->data &= 0xff00;
|
||||
s->data |= value & 0xff;
|
||||
break;
|
||||
case 0x01c: /* CPTDATH */
|
||||
s->data &= 0x00ff;
|
||||
s->data |= value << 8;
|
||||
break;
|
||||
case 0x020: /* CPTVSLL */
|
||||
s->vtol = value & 0xf8;
|
||||
break;
|
||||
case 0x024: /* CPTVSLH */
|
||||
s->vtsl = value & 0x9f;
|
||||
break;
|
||||
case 0x040: /* MPCTR */
|
||||
s->modem.control = value & 0x8f;
|
||||
break;
|
||||
case 0x044: /* MPMCCFR */
|
||||
s->modem.config = value & 0x7fff;
|
||||
break;
|
||||
case 0x060: /* BPCTR */
|
||||
s->bt.control = value & 0x8f;
|
||||
break;
|
||||
case 0x064: /* BPMCCFR */
|
||||
s->bt.config = value & 0x7fff;
|
||||
break;
|
||||
case 0x080: /* AMSCFR */
|
||||
s->mixer = value & 0x0fff;
|
||||
break;
|
||||
case 0x084: /* AMVCTR */
|
||||
s->gain[0] = value & 0xffff;
|
||||
break;
|
||||
case 0x088: /* AM1VCTR */
|
||||
s->gain[1] = value & 0xff7f;
|
||||
break;
|
||||
case 0x08c: /* AM2VCTR */
|
||||
s->gain[2] = value & 0xff7f;
|
||||
break;
|
||||
case 0x090: /* AM3VCTR */
|
||||
s->gain[3] = value & 0xff7f;
|
||||
break;
|
||||
case 0x094: /* ASTCTR */
|
||||
s->att = value & 0xff;
|
||||
break;
|
||||
|
||||
case 0x0b4: /* ADWR */
|
||||
s->codec.txbuf[s->codec.txlen ++] = value;
|
||||
if (unlikely(s->codec.txlen == EAC_BUF_LEN ||
|
||||
s->codec.txlen == s->codec.txavail)) {
|
||||
if (s->codec.txavail)
|
||||
omap_eac_out_empty(s);
|
||||
else
|
||||
s->codec.txlen = 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x0bc: /* AGCFR */
|
||||
s->codec.config[0] = value & 0x07ff;
|
||||
omap_eac_format_update(s);
|
||||
break;
|
||||
case 0x0c0: /* AGCTR */
|
||||
s->codec.config[1] = value & 0x780f;
|
||||
omap_eac_format_update(s);
|
||||
break;
|
||||
case 0x0c4: /* AGCFR2 */
|
||||
s->codec.config[2] = value & 0x003f;
|
||||
omap_eac_format_update(s);
|
||||
break;
|
||||
case 0x0c8: /* AGCFR3 */
|
||||
s->codec.config[3] = value & 0xffff;
|
||||
omap_eac_format_update(s);
|
||||
break;
|
||||
case 0x0cc: /* MBPDMACTR */
|
||||
case 0x0d4: /* MPDDMAWR */
|
||||
case 0x0e0: /* MPUDMAWR */
|
||||
case 0x0e8: /* BPDDMAWR */
|
||||
case 0x0f0: /* BPUDMAWR */
|
||||
break;
|
||||
|
||||
case 0x104: /* SYSCONFIG */
|
||||
if (value & (1 << 1)) /* SOFTRESET */
|
||||
omap_eac_reset(s);
|
||||
s->sysconfig = value & 0x31d;
|
||||
break;
|
||||
|
||||
default:
|
||||
OMAP_BAD_REG(addr);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
static CPUReadMemoryFunc *omap_eac_readfn[] = {
|
||||
omap_badwidth_read16,
|
||||
omap_eac_read,
|
||||
omap_badwidth_read16,
|
||||
};
|
||||
|
||||
static CPUWriteMemoryFunc *omap_eac_writefn[] = {
|
||||
omap_badwidth_write16,
|
||||
omap_eac_write,
|
||||
omap_badwidth_write16,
|
||||
};
|
||||
|
||||
struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
|
||||
qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
|
||||
{
|
||||
int iomemtype;
|
||||
struct omap_eac_s *s = (struct omap_eac_s *)
|
||||
qemu_mallocz(sizeof(struct omap_eac_s));
|
||||
|
||||
s->irq = irq;
|
||||
s->codec.rxdrq = *drq ++;
|
||||
s->codec.txdrq = *drq ++;
|
||||
omap_eac_reset(s);
|
||||
|
||||
#ifdef HAS_AUDIO
|
||||
/* TODO: do AUD_init globally for machine */
|
||||
AUD_register_card(AUD_init(), "OMAP EAC", &s->codec.card);
|
||||
|
||||
iomemtype = cpu_register_io_memory(0, omap_eac_readfn,
|
||||
omap_eac_writefn, s);
|
||||
s->base = omap_l4_attach(ta, 0, iomemtype);
|
||||
#endif
|
||||
|
||||
return s;
|
||||
}
|
||||
|
||||
/* STI/XTI (emulation interface) console - reverse engineered only */
|
||||
struct omap_sti_s {
|
||||
target_phys_addr_t base;
|
||||
|
|
@ -2566,6 +3102,7 @@ static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
|
|||
case 0x200: /* CM_FCLKEN1_CORE */
|
||||
s->clken[0] = value & 0xbfffffff;
|
||||
/* TODO update clocks */
|
||||
/* The EN_EAC bit only gets/puts func_96m_clk. */
|
||||
break;
|
||||
case 0x204: /* CM_FCLKEN2_CORE */
|
||||
s->clken[1] = value & 0x00000007;
|
||||
|
|
@ -2574,6 +3111,7 @@ static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
|
|||
case 0x210: /* CM_ICLKEN1_CORE */
|
||||
s->clken[2] = value & 0xfffffff9;
|
||||
/* TODO update clocks */
|
||||
/* The EN_EAC bit only gets/puts core_l4_iclk. */
|
||||
break;
|
||||
case 0x214: /* CM_ICLKEN2_CORE */
|
||||
s->clken[3] = value & 0x00000007;
|
||||
|
|
@ -3969,12 +4507,12 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
|
|||
omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk"));
|
||||
|
||||
s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4,
|
||||
s->irq[0][OMAP_INT_24XX_MCSPI1_IRQ],
|
||||
s->irq[0][OMAP_INT_24XX_MCSPI1_IRQ],
|
||||
&s->drq[OMAP24XX_DMA_SPI1_TX0],
|
||||
omap_findclk(s, "spi1_fclk"),
|
||||
omap_findclk(s, "spi1_iclk"));
|
||||
s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2,
|
||||
s->irq[0][OMAP_INT_24XX_MCSPI2_IRQ],
|
||||
s->irq[0][OMAP_INT_24XX_MCSPI2_IRQ],
|
||||
&s->drq[OMAP24XX_DMA_SPI2_TX0],
|
||||
omap_findclk(s, "spi2_fclk"),
|
||||
omap_findclk(s, "spi2_iclk"));
|
||||
|
|
@ -3992,6 +4530,13 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
|
|||
serial_hds[0] && serial_hds[1] && serial_hds[2] ?
|
||||
serial_hds[3] : 0);
|
||||
|
||||
s->eac = omap_eac_init(omap_l4ta(s->l4, 32),
|
||||
s->irq[0][OMAP_INT_24XX_EAC_IRQ],
|
||||
/* Ten consecutive lines */
|
||||
&s->drq[OMAP24XX_DMA_EAC_AC_RD],
|
||||
omap_findclk(s, "func_96m_clk"),
|
||||
omap_findclk(s, "core_l4_iclk"));
|
||||
|
||||
/* All register mappings (includin those not currenlty implemented):
|
||||
* SystemControlMod 48000000 - 48000fff
|
||||
* SystemControlL4 48001000 - 48001fff
|
||||
|
|
|
|||
Loading…
Reference in a new issue