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target/hppa: Clean up conversion from/to MMU index and privilege level
Make the conversion between privilege level and QEMU MMU index consistent, and afterwards switch to MMU indices 11-15. Signed-off-by: Helge Deller <deller@gmx.de> -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCZOtpFAAKCRD3ErUQojoP X0lxAPwKfsMZOO/e81XXLgxeEZ5R4yjtIelErvOWmMvBfxEDUwEA6HgJt4gOe1uR Dw7d+wTqr+CSOj5I87+sJYl1FmihzQU= =01eA -----END PGP SIGNATURE----- Merge tag 'devel-hppa-priv-cleanup2-pull-request' of https://github.com/hdeller/qemu-hppa into staging target/hppa: Clean up conversion from/to MMU index and privilege level Make the conversion between privilege level and QEMU MMU index consistent, and afterwards switch to MMU indices 11-15. Signed-off-by: Helge Deller <deller@gmx.de> # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCZOtpFAAKCRD3ErUQojoP # X0lxAPwKfsMZOO/e81XXLgxeEZ5R4yjtIelErvOWmMvBfxEDUwEA6HgJt4gOe1uR # Dw7d+wTqr+CSOj5I87+sJYl1FmihzQU= # =01eA # -----END PGP SIGNATURE----- # gpg: Signature made Sun 27 Aug 2023 11:17:40 EDT # gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F # gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown] # gpg: aka "Helge Deller <deller@kernel.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603 # Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F * tag 'devel-hppa-priv-cleanup2-pull-request' of https://github.com/hdeller/qemu-hppa: target/hppa: Switch to use MMU indices 11-15 target/hppa: Use privilege helper in hppa_get_physical_address() target/hppa: Do not use hardcoded value for tlb_flush_*() target/hppa: Add privilege to MMU index conversion helpers target/hppa: Add missing PL1 and PL2 privilege levels Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
commit
98bdf241be
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@ -30,11 +30,22 @@
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basis. It's probably easier to fall back to a strong memory model. */
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#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
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#define MMU_KERNEL_IDX 0
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#define MMU_USER_IDX 3
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#define MMU_PHYS_IDX 4
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#define MMU_KERNEL_IDX 11
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#define MMU_PL1_IDX 12
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#define MMU_PL2_IDX 13
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#define MMU_USER_IDX 14
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#define MMU_PHYS_IDX 15
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#define PRIV_TO_MMU_IDX(priv) (MMU_KERNEL_IDX + (priv))
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#define MMU_IDX_TO_PRIV(mmu_idx) ((mmu_idx) - MMU_KERNEL_IDX)
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#define TARGET_INSN_START_EXTRA_WORDS 1
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/* No need to flush MMU_PHYS_IDX */
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#define HPPA_MMU_FLUSH_MASK \
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(1 << MMU_KERNEL_IDX | 1 << MMU_PL1_IDX | \
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1 << MMU_PL2_IDX | 1 << MMU_USER_IDX)
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/* Hardware exceptions, interrupts, faults, and traps. */
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#define EXCP_HPMC 1 /* high priority machine check */
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#define EXCP_POWER_FAIL 2
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@ -233,7 +244,7 @@ static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
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return MMU_USER_IDX;
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#else
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if (env->psw & (ifetch ? PSW_C : PSW_D)) {
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return env->iaoq_f & 3;
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return PRIV_TO_MMU_IDX(env->iaoq_f & 3);
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}
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return MMU_PHYS_IDX; /* mmu disabled */
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#endif
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@ -71,7 +71,7 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw)
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/* If PSW_P changes, it affects how we translate addresses. */
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if ((psw ^ old_psw) & PSW_P) {
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#ifndef CONFIG_USER_ONLY
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tlb_flush_by_mmuidx(env_cpu(env), 0xf);
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tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK);
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#endif
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}
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}
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@ -50,8 +50,7 @@ static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent)
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trace_hppa_tlb_flush_ent(env, ent, ent->va_b, ent->va_e, ent->pa);
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for (i = 0; i < n; ++i, addr += TARGET_PAGE_SIZE) {
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/* Do not flush MMU_PHYS_IDX. */
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tlb_flush_page_by_mmuidx(cs, addr, 0xf);
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tlb_flush_page_by_mmuidx(cs, addr, HPPA_MMU_FLUSH_MASK);
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}
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memset(ent, 0, sizeof(*ent));
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@ -74,7 +73,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
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int type, hwaddr *pphys, int *pprot)
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{
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hwaddr phys;
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int prot, r_prot, w_prot, x_prot;
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int prot, r_prot, w_prot, x_prot, priv;
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hppa_tlb_entry *ent;
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int ret = -1;
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@ -98,9 +97,10 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
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phys = ent->pa + (addr & ~TARGET_PAGE_MASK);
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/* Map TLB access_rights field to QEMU protection. */
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r_prot = (mmu_idx <= ent->ar_pl1) * PAGE_READ;
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w_prot = (mmu_idx <= ent->ar_pl2) * PAGE_WRITE;
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x_prot = (ent->ar_pl2 <= mmu_idx && mmu_idx <= ent->ar_pl1) * PAGE_EXEC;
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priv = MMU_IDX_TO_PRIV(mmu_idx);
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r_prot = (priv <= ent->ar_pl1) * PAGE_READ;
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w_prot = (priv <= ent->ar_pl2) * PAGE_WRITE;
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x_prot = (ent->ar_pl2 <= priv && priv <= ent->ar_pl1) * PAGE_EXEC;
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switch (ent->ar_type) {
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case 0: /* read-only: data page */
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prot = r_prot;
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@ -335,13 +335,13 @@ void HELPER(ptlbe)(CPUHPPAState *env)
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{
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trace_hppa_tlb_ptlbe(env);
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memset(env->tlb, 0, sizeof(env->tlb));
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tlb_flush_by_mmuidx(env_cpu(env), 0xf);
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tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK);
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}
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void cpu_hppa_change_prot_id(CPUHPPAState *env)
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{
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if (env->psw & PSW_P) {
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tlb_flush_by_mmuidx(env_cpu(env), 0xf);
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tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK);
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}
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}
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@ -4057,14 +4057,15 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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ctx->tb_flags = ctx->base.tb->flags;
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#ifdef CONFIG_USER_ONLY
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ctx->privilege = MMU_USER_IDX;
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ctx->privilege = MMU_IDX_TO_PRIV(MMU_USER_IDX);
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ctx->mmu_idx = MMU_USER_IDX;
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ctx->iaoq_f = ctx->base.pc_first | MMU_USER_IDX;
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ctx->iaoq_b = ctx->base.tb->cs_base | MMU_USER_IDX;
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ctx->iaoq_f = ctx->base.pc_first | ctx->privilege;
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ctx->iaoq_b = ctx->base.tb->cs_base | ctx->privilege;
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ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN);
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#else
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ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3;
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ctx->mmu_idx = (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_IDX);
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ctx->mmu_idx = (ctx->tb_flags & PSW_D ?
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PRIV_TO_MMU_IDX(ctx->privilege) : MMU_PHYS_IDX);
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/* Recover the IAOQ values from the GVA + PRIV. */
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uint64_t cs_base = ctx->base.tb->cs_base;
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