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hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constant
The GIC_MIN_BPR constant defines the minimum BPR value that the TCG emulated GICv3 supports. We're currently using this also as the value we reset the KVM GICv3 ICC_BPR registers to, but this is only right by accident. We want to make the emulated GICv3 use a configurable number of priority bits, which means that GIC_MIN_BPR will no longer be a constant. Replace the uses in the KVM reset code with literal 0, plus a constant explaining why this is reasonable. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220512151457.3899052-4-peter.maydell@linaro.org Message-id: 20220506162129.2896966-3-peter.maydell@linaro.org
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@ -673,9 +673,19 @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
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s = c->gic;
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c->icc_pmr_el1 = 0;
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c->icc_bpr[GICV3_G0] = GIC_MIN_BPR;
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c->icc_bpr[GICV3_G1] = GIC_MIN_BPR;
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c->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR;
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/*
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* Architecturally the reset value of the ICC_BPR registers
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* is UNKNOWN. We set them all to 0 here; when the kernel
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* uses these values to program the ICH_VMCR_EL2 fields that
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* determine the guest-visible ICC_BPR register values, the
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* hardware's "writing a value less than the minimum sets
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* the field to the minimum value" behaviour will result in
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* them effectively resetting to the correct minimum value
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* for the host GIC.
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*/
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c->icc_bpr[GICV3_G0] = 0;
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c->icc_bpr[GICV3_G1] = 0;
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c->icc_bpr[GICV3_G1NS] = 0;
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c->icc_sre_el1 = 0x7;
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memset(c->icc_apr, 0, sizeof(c->icc_apr));
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