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tcg: Introduce tcg_set_insn_start_param

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The parameters for tcg_gen_insn_start are target_ulong, which may be split
into two TCGArg parameters for storage in the opcode on 32-bit hosts.

Fixes the ARM target and its direct use of tcg_set_insn_param, which would
set the wrong argument in the 64-on-32 case.

Cc: qemu-stable@nongnu.org
Reported-by: alarson@ddci.com
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180410003558.2470-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2018-04-10 13:02:26 +01:00 committed by Peter Maydell
parent 7f0f4208b3
commit 9743cd5736
2 changed files with 11 additions and 1 deletions
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2
target/arm/translate.h
View file

@ -120,7 +120,7 @@ static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
/* We check and clear insn_start_idx to catch multiple updates. */ /* We check and clear insn_start_idx to catch multiple updates. */
assert(s->insn_start != NULL); assert(s->insn_start != NULL);
tcg_set_insn_param(s->insn_start, 2, syn); tcg_set_insn_start_param(s->insn_start, 2, syn);
s->insn_start = NULL; s->insn_start = NULL;
} }

10
tcg/tcg.h
View file

@ -825,6 +825,16 @@ static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v)
op->args[arg] = v; op->args[arg] = v;
} }
static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v)
{
#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
tcg_set_insn_param(op, arg, v);
#else
tcg_set_insn_param(op, arg * 2, v);
tcg_set_insn_param(op, arg * 2 + 1, v >> 32);
#endif
}
/* The last op that was emitted. */ /* The last op that was emitted. */
static inline TCGOp *tcg_last_op(void) static inline TCGOp *tcg_last_op(void)
{ {