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https://gitlab.com/qemu-project/qemu
synced 2024-09-06 18:05:37 +00:00
Move interrupt_request and user_mode_only to common cpu state.
Save and restore env->interrupt_request and env->halted. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4817 c046a42c-6fe2-441c-8c8c-71466251a162
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a5cdf95220
commit
9656f324d2
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@ -153,7 +153,8 @@ typedef struct icount_decr_u16 {
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accessed */ \
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target_ulong mem_io_vaddr; /* target virtual addr at which the \
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memory was accessed */ \
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int halted; /* TRUE if the CPU is in suspend state */ \
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uint32_t halted; /* Nonzero if the CPU is in suspend state */ \
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uint32_t interrupt_request; \
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/* The meaning of the MMU modes is defined in the target code. */ \
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CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
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target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
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@ -188,6 +189,8 @@ typedef struct icount_decr_u16 {
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jmp_buf jmp_env; \
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int exception_index; \
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\
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int user_mode_only; \
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\
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void *next_cpu; /* next CPU sharing TB cache */ \
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int cpu_index; /* CPU index (informative) */ \
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int running; /* Nonzero if cpu is currently running(usermode). */ \
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29
exec.c
29
exec.c
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@ -443,6 +443,33 @@ void cpu_exec_init_all(unsigned long tb_size)
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#endif
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}
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#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
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#define CPU_COMMON_SAVE_VERSION 1
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static void cpu_common_save(QEMUFile *f, void *opaque)
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{
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CPUState *env = opaque;
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qemu_put_be32s(f, &env->halted);
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qemu_put_be32s(f, &env->interrupt_request);
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}
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static int cpu_common_load(QEMUFile *f, void *opaque, int version_id)
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{
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CPUState *env = opaque;
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if (version_id != CPU_COMMON_SAVE_VERSION)
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return -EINVAL;
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qemu_get_be32s(f, &env->halted);
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qemu_put_be32s(f, &env->interrupt_request);
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tlb_flush(env, 1);
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return 0;
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}
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#endif
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void cpu_exec_init(CPUState *env)
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{
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CPUState **penv;
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@ -459,6 +486,8 @@ void cpu_exec_init(CPUState *env)
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env->nb_watchpoints = 0;
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*penv = env;
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#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
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register_savevm("cpu_common", cpu_index, CPU_COMMON_SAVE_VERSION,
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cpu_common_save, cpu_common_load, env);
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register_savevm("cpu", cpu_index, CPU_SAVE_VERSION,
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cpu_save, cpu_load, env);
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#endif
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@ -282,11 +282,9 @@ struct CPUAlphaState {
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/* Those resources are used only in Qemu core */
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CPU_COMMON
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int user_mode_only; /* user mode only simulation */
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uint32_t hflags;
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int error_code;
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int interrupt_request;
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uint32_t features;
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uint32_t amask;
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@ -156,10 +156,6 @@ typedef struct CPUARMState {
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int (*get_irq_vector)(struct CPUARMState *);
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void *irq_opaque;
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/* exception/interrupt handling */
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int interrupt_request;
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int user_mode_only;
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/* VFP coprocessor state. */
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struct {
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float64 regs[32];
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@ -125,7 +125,6 @@ typedef struct CPUCRISState {
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/* X flag at the time of cc snapshot. */
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int cc_x;
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int interrupt_request;
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int interrupt_vector;
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int fault_vector;
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int trap_vector;
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@ -156,8 +155,6 @@ typedef struct CPUCRISState {
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uint32_t lo;
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} tlbsets[2][4][16];
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int user_mode_only;
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CPU_COMMON
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} CPUCRISState;
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@ -567,8 +567,6 @@ typedef struct CPUX86State {
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target_ulong exception_next_eip;
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target_ulong dr[8]; /* debug registers */
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uint32_t smbase;
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int interrupt_request;
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int user_mode_only; /* user mode only simulation */
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int old_exception; /* exception in flight */
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CPU_COMMON
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@ -726,7 +724,7 @@ static inline int cpu_get_time_fast(void)
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#define cpu_signal_handler cpu_x86_signal_handler
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#define cpu_list x86_cpu_list
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#define CPU_SAVE_VERSION 5
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#define CPU_SAVE_VERSION 6
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _kernel
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@ -123,7 +123,6 @@ void cpu_save(QEMUFile *f, void *opaque)
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qemu_put_be64s(f, &env->pat);
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qemu_put_be32s(f, &env->hflags2);
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qemu_put_be32s(f, (uint32_t *)&env->halted);
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qemu_put_be64s(f, &env->vm_hsave);
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qemu_put_be64s(f, &env->vm_vmcb);
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@ -169,7 +168,8 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
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uint16_t fpus, fpuc, fptag, fpregs_format;
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int32_t a20_mask;
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if (version_id != 3 && version_id != 4 && version_id != 5)
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if (version_id != 3 && version_id != 4 && version_id != 5
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&& version_id != 6)
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return -EINVAL;
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for(i = 0; i < CPU_NB_REGS; i++)
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qemu_get_betls(f, &env->regs[i]);
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@ -279,7 +279,8 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
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if (version_id >= 5) {
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qemu_get_be64s(f, &env->pat);
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qemu_get_be32s(f, &env->hflags2);
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qemu_get_be32s(f, (uint32_t *)&env->halted);
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if (version_id < 6)
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qemu_get_be32s(f, &env->halted);
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qemu_get_be64s(f, &env->vm_hsave);
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qemu_get_be64s(f, &env->vm_vmcb);
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@ -103,10 +103,6 @@ typedef struct CPUM68KState {
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/* ??? remove this. */
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uint32_t t1;
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/* exception/interrupt handling */
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int interrupt_request;
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int user_mode_only;
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int pending_vector;
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int pending_level;
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@ -411,9 +411,7 @@ struct CPUMIPSState {
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/* We waste some space so we can handle shadow registers like TCs. */
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TCState tcs[MIPS_SHADOW_SET_MAX];
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/* Qemu */
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int interrupt_request;
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int error_code;
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int user_mode_only; /* user mode only simulation */
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uint32_t hflags; /* CPU State */
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/* TMASK defines different execution modes */
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#define MIPS_HFLAG_TMASK 0x01FF
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@ -647,7 +647,6 @@ struct CPUPPCState {
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uint32_t flags;
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int error_code;
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int interrupt_request;
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uint32_t pending_interrupts;
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#if !defined(CONFIG_USER_ONLY)
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/* This is the IRQ controller, which is implementation dependant
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@ -671,7 +670,6 @@ struct CPUPPCState {
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opc_handler_t *opcodes[0x40];
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/* Those resources are used only in Qemu core */
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int user_mode_only; /* user mode only simulation */
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target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
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target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
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int mmu_idx; /* precomputed MMU index to speed up mem accesses */
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@ -114,8 +114,6 @@ typedef struct CPUSH4State {
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uint32_t expevt; /* exception event register */
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uint32_t intevt; /* interrupt event register */
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int user_mode_only;
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int interrupt_request;
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CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
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tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
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void *intc_handle;
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@ -215,9 +215,7 @@ typedef struct CPUSPARCState {
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uint32_t pil_in; /* incoming interrupt level bitmap */
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int psref; /* enable fpu */
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target_ulong version;
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int user_mode_only;
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int interrupt_index;
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int interrupt_request;
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uint32_t mmu_bm;
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uint32_t mmu_ctpr_mask;
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uint32_t mmu_cxr_mask;
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