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https://gitlab.com/qemu-project/qemu
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target-*: Increment num_insns immediately after tcg_gen_insn_start
This does tidy the icount test common to all targets. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
parent
667b8e29c5
commit
959082fc4a
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@ -2934,12 +2934,12 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu,
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tcg_ctx.gen_opc_icount[lj] = num_insns;
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}
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tcg_gen_insn_start(ctx.pc);
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num_insns++;
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if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
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if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
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gen_io_start();
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}
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insn = cpu_ldl_code(env, ctx.pc);
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num_insns++;
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TCGV_UNUSED_I64(ctx.zero);
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TCGV_UNUSED_I64(ctx.sink);
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@ -11104,8 +11104,9 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
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tcg_ctx.gen_opc_icount[lj] = num_insns;
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}
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tcg_gen_insn_start(dc->pc);
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num_insns++;
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if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
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if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
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gen_io_start();
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}
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@ -11120,7 +11121,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
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* "did not step an insn" case, and so the syndrome ISV and EX
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* bits should be zero.
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*/
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assert(num_insns == 0);
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assert(num_insns == 1);
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gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),
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default_exception_el(dc));
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dc->is_jmp = DISAS_EXC;
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@ -11139,7 +11140,6 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
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* Also stop translation when a page boundary is reached. This
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* ensures prefetch aborts occur at the right place.
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*/
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num_insns++;
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} while (!dc->is_jmp && !tcg_op_buf_full() &&
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!cs->singlestep_enabled &&
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!singlestep &&
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@ -11349,9 +11349,11 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
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tcg_ctx.gen_opc_icount[lj] = num_insns;
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}
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tcg_gen_insn_start(dc->pc);
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num_insns++;
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if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
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if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
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gen_io_start();
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}
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if (dc->ss_active && !dc->pstate_ss) {
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/* Singlestep state is Active-pending.
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@ -11364,7 +11366,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
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* "did not step an insn" case, and so the syndrome ISV and EX
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* bits should be zero.
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*/
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assert(num_insns == 0);
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assert(num_insns == 1);
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gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),
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default_exception_el(dc));
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goto done_generating;
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@ -11400,7 +11402,6 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
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* Otherwise the subsequent code could get translated several times.
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* Also stop translation when a page boundary is reached. This
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* ensures prefetch aborts occur at the right place. */
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num_insns ++;
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} while (!dc->is_jmp && !tcg_op_buf_full() &&
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!cs->singlestep_enabled &&
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!singlestep &&
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@ -3194,11 +3194,12 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
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tcg_ctx.gen_opc_icount[lj] = num_insns;
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}
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tcg_gen_insn_start(dc->pc);
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num_insns++;
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/* Pretty disas. */
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LOG_DIS("%8.8x:\t", dc->pc);
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if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
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if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
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gen_io_start();
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}
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dc->clear_x = 1;
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@ -3210,7 +3211,6 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
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cris_clear_x_flag(dc);
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}
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num_insns++;
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/* Check for delayed branches here. If we do it before
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actually generating any host code, the simulator will just
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loop doing nothing for on this program location. */
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@ -7960,12 +7960,13 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
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tcg_ctx.gen_opc_icount[lj] = num_insns;
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}
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tcg_gen_insn_start(pc_ptr);
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num_insns++;
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if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
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if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
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gen_io_start();
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}
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pc_ptr = disas_insn(env, dc, pc_ptr);
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num_insns++;
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/* stop translation if indicated */
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if (dc->is_jmp)
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break;
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@ -1103,18 +1103,17 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
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tcg_ctx.gen_opc_icount[lj] = num_insns;
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}
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tcg_gen_insn_start(dc->pc);
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num_insns++;
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/* Pretty disas. */
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LOG_DIS("%8.8x:\t", dc->pc);
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if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
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if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
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gen_io_start();
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}
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decode(dc, cpu_ldl_code(env, dc->pc));
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dc->pc += 4;
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num_insns++;
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} while (!dc->is_jmp
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&& !tcg_op_buf_full()
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&& !cs->singlestep_enabled
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@ -3022,14 +3022,14 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
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tcg_ctx.gen_opc_icount[lj] = num_insns;
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}
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tcg_gen_insn_start(dc->pc);
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num_insns++;
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if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
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if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
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gen_io_start();
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}
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dc->insn_pc = dc->pc;
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disas_m68k_insn(env, dc);
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num_insns++;
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} while (!dc->is_jmp && !tcg_op_buf_full() &&
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!cs->singlestep_enabled &&
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!singlestep &&
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@ -1715,19 +1715,20 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
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tcg_ctx.gen_opc_icount[lj] = num_insns;
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}
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tcg_gen_insn_start(dc->pc);
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num_insns++;
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/* Pretty disas. */
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LOG_DIS("%8.8x:\t", dc->pc);
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if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
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if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
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gen_io_start();
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}
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dc->clear_imm = 1;
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decode(dc, cpu_ldl_code(env, dc->pc));
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if (dc->clear_imm)
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dc->tb_flags &= ~IMM_FLAG;
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dc->pc += 4;
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num_insns++;
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if (dc->delayed_branch) {
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dc->delayed_branch--;
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@ -19619,8 +19619,9 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
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tcg_ctx.gen_opc_icount[lj] = num_insns;
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}
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tcg_gen_insn_start(ctx.pc);
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num_insns++;
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if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
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if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
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gen_io_start();
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}
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@ -19659,8 +19660,6 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
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}
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ctx.pc += insn_bytes;
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num_insns++;
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/* Execute a branch and its delay slot as a single instruction.
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This is what GDB expects and is consistent with what the
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hardware does (e.g. if a delay slot instruction faults, the
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@ -862,10 +862,10 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
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tcg_ctx.gen_opc_icount[lj] = num_insns;
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}
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tcg_gen_insn_start(ctx.pc);
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num_insns++;
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ctx.opcode = cpu_lduw_code(env, ctx.pc);
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ctx.pc += decode_opc(cpu, &ctx);
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num_insns++;
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if (cs->singlestep_enabled) {
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break;
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@ -1688,8 +1688,9 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
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tcg_ctx.gen_opc_icount[k] = num_insns;
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}
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tcg_gen_insn_start(dc->pc);
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num_insns++;
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if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
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if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
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gen_io_start();
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}
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dc->ppc = dc->pc - 4;
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@ -1698,7 +1699,6 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
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tcg_gen_movi_tl(cpu_npc, dc->npc);
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disas_openrisc_insn(dc, cpu);
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dc->pc = dc->npc;
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num_insns++;
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/* delay slot */
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if (dc->delayed_branch) {
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dc->delayed_branch--;
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@ -11503,11 +11503,12 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
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tcg_ctx.gen_opc_icount[lj] = num_insns;
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}
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tcg_gen_insn_start(ctx.nip);
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num_insns++;
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LOG_DISAS("----------------\n");
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LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
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ctx.nip, ctx.mem_idx, (int)msr_ir);
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if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
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if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
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gen_io_start();
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if (unlikely(need_byteswap(&ctx))) {
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ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
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@ -11519,7 +11520,6 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
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opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
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ctx.nip += 4;
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table = env->opcodes;
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num_insns++;
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handler = table[opc1(ctx.opcode)];
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if (is_indirect_opcode(handler)) {
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table = ind_table(handler);
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@ -5371,8 +5371,9 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu,
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tcg_ctx.gen_opc_icount[lj] = num_insns;
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}
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tcg_gen_insn_start(dc.pc);
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num_insns++;
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if (++num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
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if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
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gen_io_start();
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}
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@ -1873,14 +1873,14 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb,
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tcg_ctx.gen_opc_icount[ii] = num_insns;
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}
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tcg_gen_insn_start(ctx.pc);
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num_insns++;
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if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
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if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
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gen_io_start();
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}
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ctx.opcode = cpu_lduw_code(env, ctx.pc);
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decode_opc(&ctx);
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num_insns++;
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ctx.pc += 2;
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if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
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break;
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@ -5268,8 +5268,9 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
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}
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}
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tcg_gen_insn_start(dc->pc);
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num_insns++;
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if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
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if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
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gen_io_start();
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}
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insn = cpu_ldl_code(env, dc->pc);
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disas_sparc_insn(dc, insn);
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num_insns++;
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if (dc->is_br)
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break;
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@ -2097,6 +2097,7 @@ static inline void gen_intermediate_code_internal(TileGXCPU *cpu,
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tcg_ctx.gen_opc_icount[lj] = num_insns;
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}
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tcg_gen_insn_start(dc->pc);
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num_insns++;
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translate_one_bundle(dc, cpu_ldq_data(env, dc->pc));
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break;
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}
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dc->pc += TILEGX_BUNDLE_SIZE_IN_BYTES;
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if (++num_insns >= max_insns
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if (num_insns >= max_insns
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|| dc->pc >= next_page_start
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|| tcg_op_buf_full()) {
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/* Ending the TB due to TB size or page boundary. Set PC. */
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@ -8293,12 +8293,11 @@ gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb,
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gen_tb_start(tb);
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while (ctx.bstate == BS_NONE) {
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tcg_gen_insn_start(ctx.pc);
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num_insns++;
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ctx.opcode = cpu_ldl_code(env, ctx.pc);
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decode_opc(env, &ctx, 0);
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num_insns++;
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if (tcg_op_buf_full()) {
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gen_save_pc(ctx.next_pc);
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tcg_gen_exit_tb(0);
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@ -1938,8 +1938,9 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
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tcg_ctx.gen_opc_icount[lj] = num_insns;
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}
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tcg_gen_insn_start(dc->pc);
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num_insns++;
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if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
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if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
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gen_io_start();
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}
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@ -1958,7 +1959,6 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
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* Otherwise the subsequent code could get translated several times.
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* Also stop translation when a page boundary is reached. This
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* ensures prefetch aborts occur at the right place. */
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num_insns++;
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} while (!dc->is_jmp && !tcg_op_buf_full() &&
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!cs->singlestep_enabled &&
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!singlestep &&
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@ -3077,10 +3077,11 @@ void gen_intermediate_code_internal(XtensaCPU *cpu,
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tcg_ctx.gen_opc_icount[lj] = insn_count;
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}
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tcg_gen_insn_start(dc.pc);
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++insn_count;
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++dc.ccount_delta;
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if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
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if (insn_count == max_insns && (tb->cflags & CF_LAST_IO)) {
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gen_io_start();
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}
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@ -3101,7 +3102,6 @@ void gen_intermediate_code_internal(XtensaCPU *cpu,
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}
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disas_xtensa_insn(env, &dc);
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++insn_count;
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if (dc.icount) {
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tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
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}
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