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hw/arm: Add the USART to the stm32l4x5 SoC
Add the USART to the SoC and connect it to the other implemented devices. Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240329174402.60382-5-arnaud.minier@telecom-paris.fr [PMM: fixed a few checkpatch nits] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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92741432ed
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@ -19,13 +19,13 @@ Currently B-L475E-IOT01A machine's only supports the following devices:
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- STM32L4x5 SYSCFG (System configuration controller)
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- STM32L4x5 SYSCFG (System configuration controller)
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- STM32L4x5 RCC (Reset and clock control)
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- STM32L4x5 RCC (Reset and clock control)
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- STM32L4x5 GPIOs (General-purpose I/Os)
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- STM32L4x5 GPIOs (General-purpose I/Os)
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- STM32L4x5 USARTs, UARTs and LPUART (Serial ports)
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Missing devices
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Missing devices
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"""""""""""""""
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"""""""""""""""
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The B-L475E-IOT01A does *not* support the following devices:
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The B-L475E-IOT01A does *not* support the following devices:
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- Serial ports (UART)
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- Analog to Digital Converter (ADC)
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- Analog to Digital Converter (ADC)
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- SPI controller
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- SPI controller
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- Timer controller (TIMER)
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- Timer controller (TIMER)
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@ -477,6 +477,7 @@ config STM32L4X5_SOC
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select STM32L4X5_SYSCFG
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select STM32L4X5_SYSCFG
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select STM32L4X5_RCC
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select STM32L4X5_RCC
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select STM32L4X5_GPIO
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select STM32L4X5_GPIO
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select STM32L4X5_USART
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config XLNX_ZYNQMP_ARM
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config XLNX_ZYNQMP_ARM
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bool
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bool
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@ -28,6 +28,7 @@
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#include "sysemu/sysemu.h"
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#include "sysemu/sysemu.h"
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#include "hw/or-irq.h"
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#include "hw/or-irq.h"
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#include "hw/arm/stm32l4x5_soc.h"
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#include "hw/arm/stm32l4x5_soc.h"
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#include "hw/char/stm32l4x5_usart.h"
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#include "hw/gpio/stm32l4x5_gpio.h"
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#include "hw/gpio/stm32l4x5_gpio.h"
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#include "hw/qdev-clock.h"
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#include "hw/qdev-clock.h"
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#include "hw/misc/unimp.h"
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#include "hw/misc/unimp.h"
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@ -116,6 +117,22 @@ static const struct {
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{ 0x48001C00, 0x0000000F, 0x00000000, 0x00000000 },
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{ 0x48001C00, 0x0000000F, 0x00000000, 0x00000000 },
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};
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};
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static const hwaddr usart_addr[] = {
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0x40013800, /* "USART1", 0x400 */
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0x40004400, /* "USART2", 0x400 */
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0x40004800, /* "USART3", 0x400 */
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};
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static const hwaddr uart_addr[] = {
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0x40004C00, /* "UART4" , 0x400 */
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0x40005000 /* "UART5" , 0x400 */
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};
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#define LPUART_BASE_ADDRESS 0x40008000
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static const int usart_irq[] = { 37, 38, 39 };
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static const int uart_irq[] = { 52, 53 };
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#define LPUART_IRQ 70
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static void stm32l4x5_soc_initfn(Object *obj)
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static void stm32l4x5_soc_initfn(Object *obj)
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{
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{
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Stm32l4x5SocState *s = STM32L4X5_SOC(obj);
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Stm32l4x5SocState *s = STM32L4X5_SOC(obj);
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@ -132,6 +149,18 @@ static void stm32l4x5_soc_initfn(Object *obj)
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g_autofree char *name = g_strdup_printf("gpio%c", 'a' + i);
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g_autofree char *name = g_strdup_printf("gpio%c", 'a' + i);
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object_initialize_child(obj, name, &s->gpio[i], TYPE_STM32L4X5_GPIO);
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object_initialize_child(obj, name, &s->gpio[i], TYPE_STM32L4X5_GPIO);
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}
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}
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for (int i = 0; i < STM_NUM_USARTS; i++) {
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object_initialize_child(obj, "usart[*]", &s->usart[i],
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TYPE_STM32L4X5_USART);
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}
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for (int i = 0; i < STM_NUM_UARTS; i++) {
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object_initialize_child(obj, "uart[*]", &s->uart[i],
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TYPE_STM32L4X5_UART);
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}
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object_initialize_child(obj, "lpuart1", &s->lpuart,
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TYPE_STM32L4X5_LPUART);
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}
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}
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static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
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static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
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@ -279,6 +308,54 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
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sysbus_mmio_map(busdev, 0, RCC_BASE_ADDRESS);
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sysbus_mmio_map(busdev, 0, RCC_BASE_ADDRESS);
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sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, RCC_IRQ));
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sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, RCC_IRQ));
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/* USART devices */
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for (int i = 0; i < STM_NUM_USARTS; i++) {
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g_autofree char *name = g_strdup_printf("usart%d-out", i + 1);
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dev = DEVICE(&(s->usart[i]));
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qdev_prop_set_chr(dev, "chardev", serial_hd(i));
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qdev_connect_clock_in(dev, "clk",
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qdev_get_clock_out(DEVICE(&(s->rcc)), name));
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busdev = SYS_BUS_DEVICE(dev);
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if (!sysbus_realize(busdev, errp)) {
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return;
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}
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sysbus_mmio_map(busdev, 0, usart_addr[i]);
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sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
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}
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/*
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* TODO: Connect the USARTs, UARTs and LPUART to the EXTI once the EXTI
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* can handle other gpio-in than the gpios. (e.g. Direct Lines for the
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* usarts)
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*/
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/* UART devices */
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for (int i = 0; i < STM_NUM_UARTS; i++) {
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g_autofree char *name = g_strdup_printf("uart%d-out", STM_NUM_USARTS + i + 1);
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dev = DEVICE(&(s->uart[i]));
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qdev_prop_set_chr(dev, "chardev", serial_hd(STM_NUM_USARTS + i));
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qdev_connect_clock_in(dev, "clk",
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qdev_get_clock_out(DEVICE(&(s->rcc)), name));
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busdev = SYS_BUS_DEVICE(dev);
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if (!sysbus_realize(busdev, errp)) {
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return;
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}
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sysbus_mmio_map(busdev, 0, uart_addr[i]);
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sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, uart_irq[i]));
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}
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/* LPUART device*/
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dev = DEVICE(&(s->lpuart));
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qdev_prop_set_chr(dev, "chardev", serial_hd(STM_NUM_USARTS + STM_NUM_UARTS));
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qdev_connect_clock_in(dev, "clk",
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qdev_get_clock_out(DEVICE(&(s->rcc)), "lpuart1-out"));
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busdev = SYS_BUS_DEVICE(dev);
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if (!sysbus_realize(busdev, errp)) {
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return;
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}
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sysbus_mmio_map(busdev, 0, LPUART_BASE_ADDRESS);
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sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, LPUART_IRQ));
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/* APB1 BUS */
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/* APB1 BUS */
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create_unimplemented_device("TIM2", 0x40000000, 0x400);
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create_unimplemented_device("TIM2", 0x40000000, 0x400);
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create_unimplemented_device("TIM3", 0x40000400, 0x400);
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create_unimplemented_device("TIM3", 0x40000400, 0x400);
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@ -294,10 +371,6 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
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create_unimplemented_device("SPI2", 0x40003800, 0x400);
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create_unimplemented_device("SPI2", 0x40003800, 0x400);
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create_unimplemented_device("SPI3", 0x40003C00, 0x400);
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create_unimplemented_device("SPI3", 0x40003C00, 0x400);
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/* RESERVED: 0x40004000, 0x400 */
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/* RESERVED: 0x40004000, 0x400 */
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create_unimplemented_device("USART2", 0x40004400, 0x400);
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create_unimplemented_device("USART3", 0x40004800, 0x400);
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create_unimplemented_device("UART4", 0x40004C00, 0x400);
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create_unimplemented_device("UART5", 0x40005000, 0x400);
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create_unimplemented_device("I2C1", 0x40005400, 0x400);
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create_unimplemented_device("I2C1", 0x40005400, 0x400);
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create_unimplemented_device("I2C2", 0x40005800, 0x400);
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create_unimplemented_device("I2C2", 0x40005800, 0x400);
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create_unimplemented_device("I2C3", 0x40005C00, 0x400);
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create_unimplemented_device("I2C3", 0x40005C00, 0x400);
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@ -308,7 +381,6 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
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create_unimplemented_device("DAC1", 0x40007400, 0x400);
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create_unimplemented_device("DAC1", 0x40007400, 0x400);
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create_unimplemented_device("OPAMP", 0x40007800, 0x400);
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create_unimplemented_device("OPAMP", 0x40007800, 0x400);
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create_unimplemented_device("LPTIM1", 0x40007C00, 0x400);
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create_unimplemented_device("LPTIM1", 0x40007C00, 0x400);
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create_unimplemented_device("LPUART1", 0x40008000, 0x400);
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/* RESERVED: 0x40008400, 0x400 */
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/* RESERVED: 0x40008400, 0x400 */
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create_unimplemented_device("SWPMI1", 0x40008800, 0x400);
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create_unimplemented_device("SWPMI1", 0x40008800, 0x400);
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/* RESERVED: 0x40008C00, 0x800 */
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/* RESERVED: 0x40008C00, 0x800 */
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@ -325,7 +397,6 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
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create_unimplemented_device("TIM1", 0x40012C00, 0x400);
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create_unimplemented_device("TIM1", 0x40012C00, 0x400);
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create_unimplemented_device("SPI1", 0x40013000, 0x400);
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create_unimplemented_device("SPI1", 0x40013000, 0x400);
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create_unimplemented_device("TIM8", 0x40013400, 0x400);
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create_unimplemented_device("TIM8", 0x40013400, 0x400);
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create_unimplemented_device("USART1", 0x40013800, 0x400);
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/* RESERVED: 0x40013C00, 0x400 */
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/* RESERVED: 0x40013C00, 0x400 */
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create_unimplemented_device("TIM15", 0x40014000, 0x400);
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create_unimplemented_device("TIM15", 0x40014000, 0x400);
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create_unimplemented_device("TIM16", 0x40014400, 0x400);
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create_unimplemented_device("TIM16", 0x40014400, 0x400);
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@ -31,6 +31,7 @@
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#include "hw/misc/stm32l4x5_exti.h"
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#include "hw/misc/stm32l4x5_exti.h"
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#include "hw/misc/stm32l4x5_rcc.h"
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#include "hw/misc/stm32l4x5_rcc.h"
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#include "hw/gpio/stm32l4x5_gpio.h"
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#include "hw/gpio/stm32l4x5_gpio.h"
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#include "hw/char/stm32l4x5_usart.h"
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#include "qom/object.h"
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#include "qom/object.h"
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#define TYPE_STM32L4X5_SOC "stm32l4x5-soc"
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#define TYPE_STM32L4X5_SOC "stm32l4x5-soc"
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@ -41,6 +42,9 @@ OBJECT_DECLARE_TYPE(Stm32l4x5SocState, Stm32l4x5SocClass, STM32L4X5_SOC)
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#define NUM_EXTI_OR_GATES 4
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#define NUM_EXTI_OR_GATES 4
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#define STM_NUM_USARTS 3
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#define STM_NUM_UARTS 2
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struct Stm32l4x5SocState {
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struct Stm32l4x5SocState {
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SysBusDevice parent_obj;
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SysBusDevice parent_obj;
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@ -51,6 +55,9 @@ struct Stm32l4x5SocState {
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Stm32l4x5SyscfgState syscfg;
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Stm32l4x5SyscfgState syscfg;
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Stm32l4x5RccState rcc;
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Stm32l4x5RccState rcc;
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Stm32l4x5GpioState gpio[NUM_GPIOS];
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Stm32l4x5GpioState gpio[NUM_GPIOS];
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Stm32l4x5UsartBaseState usart[STM_NUM_USARTS];
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Stm32l4x5UsartBaseState uart[STM_NUM_UARTS];
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Stm32l4x5UsartBaseState lpuart;
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MemoryRegion sram1;
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MemoryRegion sram1;
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MemoryRegion sram2;
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MemoryRegion sram2;
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