diff --git a/target-mips/helper.c b/target-mips/helper.c
index d2d7a9f871..51b8ca102c 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -41,12 +41,12 @@ enum {
 static int map_address (CPUState *env, target_ulong *physical, int *prot,
                         target_ulong address, int rw, int access_type)
 {
+    uint8_t ASID = env->CP0_EntryHi & 0xFF;
     int i;
 
     for (i = 0; i < env->tlb_in_use; i++) {
         tlb_t *tlb = &env->tlb[i];
         /* 1k pages are not supported. */
-        uint8_t ASID = env->CP0_EntryHi & 0xFF;
         target_ulong mask = tlb->PageMask | 0x1FFF;
         target_ulong tag = address & ~mask;
         int n;
diff --git a/target-mips/op.c b/target-mips/op.c
index cd5c69ca46..34c17c1ab5 100644
--- a/target-mips/op.c
+++ b/target-mips/op.c
@@ -1340,7 +1340,7 @@ void op_mtc0_entryhi (void)
 
     /* 1k pages not implemented */
     /* Ignore MIPS64 TLB for now */
-    val = (int32_t)T0 & 0xFFFFE0FF;
+    val = (target_ulong)(int32_t)T0 & ~(target_ulong)0x1F00;
     old = env->CP0_EntryHi;
     env->CP0_EntryHi = val;
     /* If the ASID changes, flush qemu's TLB.  */
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 9596d04fb6..1b8d9351a9 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -395,7 +395,7 @@ static void fill_tlb (int idx)
 
     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
     tlb = &env->tlb[idx];
-    tlb->VPN = env->CP0_EntryHi & (int32_t)0xFFFFE000;
+    tlb->VPN = env->CP0_EntryHi & ~(target_ulong)0x1FFF;
     tlb->ASID = env->CP0_EntryHi & 0xFF;
     tlb->PageMask = env->CP0_PageMask;
     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;