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target/sparc: Fix FMUL8x16
This instruction has f32 as source1, which alters the decoding of the register number, which means we've been passing the wrong data for odd register numbers. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240502165528.244004-4-richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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@ -95,7 +95,7 @@ DEF_HELPER_FLAGS_2(fdtox, TCG_CALL_NO_WG, s64, env, f64)
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DEF_HELPER_FLAGS_2(fqtox, TCG_CALL_NO_WG, s64, env, i128)
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DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i32, i64)
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DEF_HELPER_FLAGS_2(fmul8x16al, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(fmul8x16au, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(fmul8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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@ -4583,6 +4583,26 @@ TRANS(FSUBs, ALL, do_env_fff, a, gen_helper_fsubs)
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TRANS(FMULs, ALL, do_env_fff, a, gen_helper_fmuls)
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TRANS(FDIVs, ALL, do_env_fff, a, gen_helper_fdivs)
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static bool do_dfd(DisasContext *dc, arg_r_r_r *a,
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void (*func)(TCGv_i64, TCGv_i32, TCGv_i64))
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{
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TCGv_i64 dst, src2;
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TCGv_i32 src1;
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if (gen_trap_ifnofpu(dc)) {
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return true;
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}
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dst = gen_dest_fpr_D(dc, a->rd);
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src1 = gen_load_fpr_F(dc, a->rs1);
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src2 = gen_load_fpr_D(dc, a->rs2);
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func(dst, src1, src2);
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gen_store_fpr_D(dc, a->rd, dst);
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return advance_pc(dc);
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}
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TRANS(FMUL8x16, VIS1, do_dfd, a, gen_helper_fmul8x16)
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static bool do_ddd(DisasContext *dc, arg_r_r_r *a,
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void (*func)(TCGv_i64, TCGv_i64, TCGv_i64))
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{
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@ -4600,7 +4620,6 @@ static bool do_ddd(DisasContext *dc, arg_r_r_r *a,
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return advance_pc(dc);
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}
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TRANS(FMUL8x16, VIS1, do_ddd, a, gen_helper_fmul8x16)
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TRANS(FMUL8x16AU, VIS1, do_ddd, a, gen_helper_fmul8x16au)
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TRANS(FMUL8x16AL, VIS1, do_ddd, a, gen_helper_fmul8x16al)
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TRANS(FMUL8SUx16, VIS1, do_ddd, a, gen_helper_fmul8sux16)
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@ -94,16 +94,17 @@ uint64_t helper_fpmerge(uint64_t src1, uint64_t src2)
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return d.ll;
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}
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uint64_t helper_fmul8x16(uint64_t src1, uint64_t src2)
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uint64_t helper_fmul8x16(uint32_t src1, uint64_t src2)
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{
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VIS64 s, d;
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VIS64 d;
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VIS32 s;
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uint32_t tmp;
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s.ll = src1;
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s.l = src1;
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d.ll = src2;
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#define PMUL(r) \
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tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
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tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B32(r); \
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if ((tmp & 0xff) > 0x7f) { \
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tmp += 0x100; \
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} \
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