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ppc/pnv: extend XSCOM core support for POWER9
Provide a new class attribute to define XSCOM operations per CPU family and add a couple of XSCOM addresses controlling the power management states of the core on POWER9. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190307223548.20516-11-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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6598a70d00
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90ef386c74
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@ -60,8 +60,8 @@ static void pnv_cpu_reset(void *opaque)
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#define PNV_XSCOM_EX_DTS_RESULT0 0x50000
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#define PNV_XSCOM_EX_DTS_RESULT0 0x50000
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#define PNV_XSCOM_EX_DTS_RESULT1 0x50001
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#define PNV_XSCOM_EX_DTS_RESULT1 0x50001
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static uint64_t pnv_core_xscom_read(void *opaque, hwaddr addr,
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static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr,
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unsigned int width)
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unsigned int width)
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{
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{
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uint32_t offset = addr >> 3;
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uint32_t offset = addr >> 3;
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uint64_t val = 0;
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uint64_t val = 0;
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@ -82,16 +82,74 @@ static uint64_t pnv_core_xscom_read(void *opaque, hwaddr addr,
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return val;
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return val;
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}
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}
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static void pnv_core_xscom_write(void *opaque, hwaddr addr, uint64_t val,
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static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned int width)
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unsigned int width)
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{
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{
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qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
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qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
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addr);
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addr);
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}
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}
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static const MemoryRegionOps pnv_core_xscom_ops = {
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static const MemoryRegionOps pnv_core_power8_xscom_ops = {
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.read = pnv_core_xscom_read,
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.read = pnv_core_power8_xscom_read,
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.write = pnv_core_xscom_write,
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.write = pnv_core_power8_xscom_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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/*
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* POWER9 core controls
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*/
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#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d
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#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a
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static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
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unsigned int width)
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{
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uint32_t offset = addr >> 3;
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uint64_t val = 0;
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/* The result should be 38 C */
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switch (offset) {
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case PNV_XSCOM_EX_DTS_RESULT0:
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val = 0x26f024f023f0000ull;
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break;
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case PNV_XSCOM_EX_DTS_RESULT1:
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val = 0x24f000000000000ull;
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break;
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case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
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case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
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val = 0x0;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
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addr);
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}
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return val;
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}
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static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned int width)
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{
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uint32_t offset = addr >> 3;
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switch (offset) {
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case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
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case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
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addr);
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}
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}
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static const MemoryRegionOps pnv_core_power9_xscom_ops = {
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.read = pnv_core_power9_xscom_read,
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.write = pnv_core_power9_xscom_write,
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.valid.min_access_size = 8,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.min_access_size = 8,
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@ -138,6 +196,7 @@ static void pnv_realize_vcpu(PowerPCCPU *cpu, PnvChip *chip, Error **errp)
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static void pnv_core_realize(DeviceState *dev, Error **errp)
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static void pnv_core_realize(DeviceState *dev, Error **errp)
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{
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{
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PnvCore *pc = PNV_CORE(OBJECT(dev));
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PnvCore *pc = PNV_CORE(OBJECT(dev));
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PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc);
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CPUCore *cc = CPU_CORE(OBJECT(dev));
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CPUCore *cc = CPU_CORE(OBJECT(dev));
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const char *typename = pnv_core_cpu_typename(pc);
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const char *typename = pnv_core_cpu_typename(pc);
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Error *local_err = NULL;
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Error *local_err = NULL;
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@ -180,7 +239,7 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
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}
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}
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snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
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snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
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pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), &pnv_core_xscom_ops,
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pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops,
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pc, name, PNV_XSCOM_EX_SIZE);
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pc, name, PNV_XSCOM_EX_SIZE);
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return;
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return;
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@ -222,6 +281,20 @@ static Property pnv_core_properties[] = {
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DEFINE_PROP_END_OF_LIST(),
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DEFINE_PROP_END_OF_LIST(),
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};
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};
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static void pnv_core_power8_class_init(ObjectClass *oc, void *data)
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{
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PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
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pcc->xscom_ops = &pnv_core_power8_xscom_ops;
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}
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static void pnv_core_power9_class_init(ObjectClass *oc, void *data)
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{
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PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
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pcc->xscom_ops = &pnv_core_power9_xscom_ops;
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}
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static void pnv_core_class_init(ObjectClass *oc, void *data)
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static void pnv_core_class_init(ObjectClass *oc, void *data)
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{
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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@ -231,10 +304,11 @@ static void pnv_core_class_init(ObjectClass *oc, void *data)
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dc->props = pnv_core_properties;
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dc->props = pnv_core_properties;
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}
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}
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#define DEFINE_PNV_CORE_TYPE(cpu_model) \
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#define DEFINE_PNV_CORE_TYPE(family, cpu_model) \
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{ \
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{ \
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.parent = TYPE_PNV_CORE, \
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.parent = TYPE_PNV_CORE, \
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.name = PNV_CORE_TYPE_NAME(cpu_model), \
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.name = PNV_CORE_TYPE_NAME(cpu_model), \
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.class_init = pnv_core_##family##_class_init, \
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}
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}
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static const TypeInfo pnv_core_infos[] = {
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static const TypeInfo pnv_core_infos[] = {
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@ -246,10 +320,10 @@ static const TypeInfo pnv_core_infos[] = {
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.class_init = pnv_core_class_init,
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.class_init = pnv_core_class_init,
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.abstract = true,
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.abstract = true,
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},
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},
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DEFINE_PNV_CORE_TYPE("power8e_v2.1"),
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DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"),
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DEFINE_PNV_CORE_TYPE("power8_v2.0"),
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DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"),
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DEFINE_PNV_CORE_TYPE("power8nvl_v1.0"),
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DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
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DEFINE_PNV_CORE_TYPE("power9_v2.0"),
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DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"),
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};
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};
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DEFINE_TYPES(pnv_core_infos)
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DEFINE_TYPES(pnv_core_infos)
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@ -42,6 +42,8 @@ typedef struct PnvCore {
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typedef struct PnvCoreClass {
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typedef struct PnvCoreClass {
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DeviceClass parent_class;
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DeviceClass parent_class;
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const MemoryRegionOps *xscom_ops;
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} PnvCoreClass;
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} PnvCoreClass;
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#define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE
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#define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE
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