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https://gitlab.com/qemu-project/qemu
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tcg: Rename TCGMemOpIdx to MemOpIdx
We're about to move this out of tcg.h, so rename it as we did when moving MemOp. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
4b473e0c60
commit
9002ffcb72
25 changed files with 177 additions and 177 deletions
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@ -14,7 +14,7 @@
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*/
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static uint16_t atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi)
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MemOpIdx oi)
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{
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CPUState *cpu = env_cpu(env);
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uint16_t info = trace_mem_get_info(get_memop(oi), get_mmuidx(oi), false);
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@ -34,7 +34,7 @@ static void atomic_trace_rmw_post(CPUArchState *env, target_ulong addr,
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#if HAVE_ATOMIC128
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static uint16_t atomic_trace_ld_pre(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi)
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MemOpIdx oi)
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{
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uint16_t info = trace_mem_get_info(get_memop(oi), get_mmuidx(oi), false);
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@ -50,7 +50,7 @@ static void atomic_trace_ld_post(CPUArchState *env, target_ulong addr,
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}
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static uint16_t atomic_trace_st_pre(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi)
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MemOpIdx oi)
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{
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uint16_t info = trace_mem_get_info(get_memop(oi), get_mmuidx(oi), true);
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@ -72,7 +72,7 @@
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ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
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ABI_TYPE cmpv, ABI_TYPE newv,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
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PAGE_READ | PAGE_WRITE, retaddr);
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@ -92,7 +92,7 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
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#if DATA_SIZE >= 16
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#if HAVE_ATOMIC128
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ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
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PAGE_READ, retaddr);
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@ -106,7 +106,7 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr,
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}
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void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
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PAGE_WRITE, retaddr);
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@ -119,7 +119,7 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
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#endif
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#else
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ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
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PAGE_READ | PAGE_WRITE, retaddr);
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@ -134,7 +134,7 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
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#define GEN_ATOMIC_HELPER(X) \
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ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
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ABI_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) \
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ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) \
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{ \
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DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
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PAGE_READ | PAGE_WRITE, retaddr); \
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@ -167,7 +167,7 @@ GEN_ATOMIC_HELPER(xor_fetch)
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*/
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#define GEN_ATOMIC_HELPER_FN(X, FN, XDATA_TYPE, RET) \
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ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
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ABI_TYPE xval, TCGMemOpIdx oi, uintptr_t retaddr) \
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ABI_TYPE xval, MemOpIdx oi, uintptr_t retaddr) \
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{ \
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XDATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
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PAGE_READ | PAGE_WRITE, retaddr); \
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@ -211,7 +211,7 @@ GEN_ATOMIC_HELPER_FN(umax_fetch, MAX, DATA_TYPE, new)
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ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
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ABI_TYPE cmpv, ABI_TYPE newv,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
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PAGE_READ | PAGE_WRITE, retaddr);
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@ -231,7 +231,7 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
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#if DATA_SIZE >= 16
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#if HAVE_ATOMIC128
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ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
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PAGE_READ, retaddr);
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@ -245,7 +245,7 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr,
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}
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void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
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PAGE_WRITE, retaddr);
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@ -259,7 +259,7 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
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#endif
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#else
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ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
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PAGE_READ | PAGE_WRITE, retaddr);
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@ -274,7 +274,7 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
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#define GEN_ATOMIC_HELPER(X) \
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ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
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ABI_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) \
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ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) \
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{ \
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DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
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PAGE_READ | PAGE_WRITE, retaddr); \
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@ -304,7 +304,7 @@ GEN_ATOMIC_HELPER(xor_fetch)
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*/
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#define GEN_ATOMIC_HELPER_FN(X, FN, XDATA_TYPE, RET) \
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ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
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ABI_TYPE xval, TCGMemOpIdx oi, uintptr_t retaddr) \
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ABI_TYPE xval, MemOpIdx oi, uintptr_t retaddr) \
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{ \
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XDATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
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PAGE_READ | PAGE_WRITE, retaddr); \
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@ -1749,7 +1749,7 @@ bool tlb_plugin_lookup(CPUState *cpu, target_ulong addr, int mmu_idx,
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* @prot may be PAGE_READ, PAGE_WRITE, or PAGE_READ|PAGE_WRITE.
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*/
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static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, int size, int prot,
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MemOpIdx oi, int size, int prot,
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uintptr_t retaddr)
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{
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size_t mmu_idx = get_mmuidx(oi);
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@ -1850,7 +1850,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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*/
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typedef uint64_t FullLoadHelper(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr);
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MemOpIdx oi, uintptr_t retaddr);
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static inline uint64_t QEMU_ALWAYS_INLINE
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load_memop(const void *haddr, MemOp op)
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@ -1876,7 +1876,7 @@ load_memop(const void *haddr, MemOp op)
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}
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static inline uint64_t QEMU_ALWAYS_INLINE
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load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
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load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi,
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uintptr_t retaddr, MemOp op, bool code_read,
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FullLoadHelper *full_load)
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{
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@ -1991,78 +1991,78 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
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*/
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static uint64_t full_ldub_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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return load_helper(env, addr, oi, retaddr, MO_UB, false, full_ldub_mmu);
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}
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tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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return full_ldub_mmu(env, addr, oi, retaddr);
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}
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static uint64_t full_le_lduw_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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return load_helper(env, addr, oi, retaddr, MO_LEUW, false,
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full_le_lduw_mmu);
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}
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tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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return full_le_lduw_mmu(env, addr, oi, retaddr);
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}
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static uint64_t full_be_lduw_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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return load_helper(env, addr, oi, retaddr, MO_BEUW, false,
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full_be_lduw_mmu);
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}
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tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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return full_be_lduw_mmu(env, addr, oi, retaddr);
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}
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static uint64_t full_le_ldul_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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return load_helper(env, addr, oi, retaddr, MO_LEUL, false,
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full_le_ldul_mmu);
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}
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tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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return full_le_ldul_mmu(env, addr, oi, retaddr);
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}
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static uint64_t full_be_ldul_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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return load_helper(env, addr, oi, retaddr, MO_BEUL, false,
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full_be_ldul_mmu);
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}
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tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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return full_be_ldul_mmu(env, addr, oi, retaddr);
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}
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uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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return load_helper(env, addr, oi, retaddr, MO_LEQ, false,
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helper_le_ldq_mmu);
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}
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uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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return load_helper(env, addr, oi, retaddr, MO_BEQ, false,
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helper_be_ldq_mmu);
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@ -2075,31 +2075,31 @@ uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
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tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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return (int8_t)helper_ret_ldub_mmu(env, addr, oi, retaddr);
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}
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tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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return (int16_t)helper_le_lduw_mmu(env, addr, oi, retaddr);
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}
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tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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return (int16_t)helper_be_lduw_mmu(env, addr, oi, retaddr);
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}
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tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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return (int32_t)helper_le_ldul_mmu(env, addr, oi, retaddr);
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}
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tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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return (int32_t)helper_be_ldul_mmu(env, addr, oi, retaddr);
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}
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@ -2113,7 +2113,7 @@ static inline uint64_t cpu_load_helper(CPUArchState *env, abi_ptr addr,
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MemOp op, FullLoadHelper *full_load)
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{
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uint16_t meminfo;
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TCGMemOpIdx oi;
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MemOpIdx oi;
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uint64_t ret;
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meminfo = trace_mem_get_info(op, mmu_idx, false);
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@ -2337,7 +2337,7 @@ store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val,
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uintptr_t index, index2;
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CPUTLBEntry *entry, *entry2;
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target_ulong page2, tlb_addr, tlb_addr2;
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TCGMemOpIdx oi;
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MemOpIdx oi;
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size_t size2;
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int i;
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@ -2404,7 +2404,7 @@ store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val,
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static inline void QEMU_ALWAYS_INLINE
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store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
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TCGMemOpIdx oi, uintptr_t retaddr, MemOp op)
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MemOpIdx oi, uintptr_t retaddr, MemOp op)
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{
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uintptr_t mmu_idx = get_mmuidx(oi);
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uintptr_t index = tlb_index(env, mmu_idx, addr);
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@ -2502,43 +2502,43 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
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void __attribute__((noinline))
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helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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store_helper(env, addr, val, oi, retaddr, MO_UB);
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}
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void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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store_helper(env, addr, val, oi, retaddr, MO_LEUW);
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}
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void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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store_helper(env, addr, val, oi, retaddr, MO_BEUW);
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}
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void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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store_helper(env, addr, val, oi, retaddr, MO_LEUL);
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}
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void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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store_helper(env, addr, val, oi, retaddr, MO_BEUL);
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}
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void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
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TCGMemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t retaddr)
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{
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store_helper(env, addr, val, oi, retaddr, MO_LEQ);
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}
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|
||||
void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr)
|
||||
MemOpIdx oi, uintptr_t retaddr)
|
||||
{
|
||||
store_helper(env, addr, val, oi, retaddr, MO_BEQ);
|
||||
}
|
||||
|
|
@ -2551,7 +2551,7 @@ static inline void QEMU_ALWAYS_INLINE
|
|||
cpu_store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
|
||||
int mmu_idx, uintptr_t retaddr, MemOp op)
|
||||
{
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
uint16_t meminfo;
|
||||
|
||||
meminfo = trace_mem_get_info(op, mmu_idx, true);
|
||||
|
|
@ -2717,49 +2717,49 @@ void cpu_stq_le_data(CPUArchState *env, target_ulong ptr, uint64_t val)
|
|||
/* Code access functions. */
|
||||
|
||||
static uint64_t full_ldub_code(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr)
|
||||
MemOpIdx oi, uintptr_t retaddr)
|
||||
{
|
||||
return load_helper(env, addr, oi, retaddr, MO_8, true, full_ldub_code);
|
||||
}
|
||||
|
||||
uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr)
|
||||
{
|
||||
TCGMemOpIdx oi = make_memop_idx(MO_UB, cpu_mmu_index(env, true));
|
||||
MemOpIdx oi = make_memop_idx(MO_UB, cpu_mmu_index(env, true));
|
||||
return full_ldub_code(env, addr, oi, 0);
|
||||
}
|
||||
|
||||
static uint64_t full_lduw_code(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr)
|
||||
MemOpIdx oi, uintptr_t retaddr)
|
||||
{
|
||||
return load_helper(env, addr, oi, retaddr, MO_TEUW, true, full_lduw_code);
|
||||
}
|
||||
|
||||
uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr)
|
||||
{
|
||||
TCGMemOpIdx oi = make_memop_idx(MO_TEUW, cpu_mmu_index(env, true));
|
||||
MemOpIdx oi = make_memop_idx(MO_TEUW, cpu_mmu_index(env, true));
|
||||
return full_lduw_code(env, addr, oi, 0);
|
||||
}
|
||||
|
||||
static uint64_t full_ldl_code(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr)
|
||||
MemOpIdx oi, uintptr_t retaddr)
|
||||
{
|
||||
return load_helper(env, addr, oi, retaddr, MO_TEUL, true, full_ldl_code);
|
||||
}
|
||||
|
||||
uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr)
|
||||
{
|
||||
TCGMemOpIdx oi = make_memop_idx(MO_TEUL, cpu_mmu_index(env, true));
|
||||
MemOpIdx oi = make_memop_idx(MO_TEUL, cpu_mmu_index(env, true));
|
||||
return full_ldl_code(env, addr, oi, 0);
|
||||
}
|
||||
|
||||
static uint64_t full_ldq_code(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr)
|
||||
MemOpIdx oi, uintptr_t retaddr)
|
||||
{
|
||||
return load_helper(env, addr, oi, retaddr, MO_TEQ, true, full_ldq_code);
|
||||
}
|
||||
|
||||
uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr)
|
||||
{
|
||||
TCGMemOpIdx oi = make_memop_idx(MO_TEQ, cpu_mmu_index(env, true));
|
||||
MemOpIdx oi = make_memop_idx(MO_TEQ, cpu_mmu_index(env, true));
|
||||
return full_ldq_code(env, addr, oi, 0);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1228,7 +1228,7 @@ uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ptr)
|
|||
* @prot may be PAGE_READ, PAGE_WRITE, or PAGE_READ|PAGE_WRITE.
|
||||
*/
|
||||
static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, int size, int prot,
|
||||
MemOpIdx oi, int size, int prot,
|
||||
uintptr_t retaddr)
|
||||
{
|
||||
/* Enforce qemu required alignment. */
|
||||
|
|
|
|||
|
|
@ -1148,7 +1148,7 @@ static inline size_t tcg_current_code_size(TCGContext *s)
|
|||
}
|
||||
|
||||
/* Combine the MemOp and mmu_idx parameters into a single value. */
|
||||
typedef uint32_t TCGMemOpIdx;
|
||||
typedef uint32_t MemOpIdx;
|
||||
|
||||
/**
|
||||
* make_memop_idx
|
||||
|
|
@ -1157,7 +1157,7 @@ typedef uint32_t TCGMemOpIdx;
|
|||
*
|
||||
* Encode these values into a single parameter.
|
||||
*/
|
||||
static inline TCGMemOpIdx make_memop_idx(MemOp op, unsigned idx)
|
||||
static inline MemOpIdx make_memop_idx(MemOp op, unsigned idx)
|
||||
{
|
||||
tcg_debug_assert(idx <= 15);
|
||||
return (op << 4) | idx;
|
||||
|
|
@ -1169,7 +1169,7 @@ static inline TCGMemOpIdx make_memop_idx(MemOp op, unsigned idx)
|
|||
*
|
||||
* Extract the memory operation from the combined value.
|
||||
*/
|
||||
static inline MemOp get_memop(TCGMemOpIdx oi)
|
||||
static inline MemOp get_memop(MemOpIdx oi)
|
||||
{
|
||||
return oi >> 4;
|
||||
}
|
||||
|
|
@ -1180,7 +1180,7 @@ static inline MemOp get_memop(TCGMemOpIdx oi)
|
|||
*
|
||||
* Extract the mmu index from the combined value.
|
||||
*/
|
||||
static inline unsigned get_mmuidx(TCGMemOpIdx oi)
|
||||
static inline unsigned get_mmuidx(MemOpIdx oi)
|
||||
{
|
||||
return oi & 15;
|
||||
}
|
||||
|
|
@ -1290,46 +1290,46 @@ uint64_t dup_const(unsigned vece, uint64_t c);
|
|||
#ifdef CONFIG_SOFTMMU
|
||||
/* Value zero-extended to tcg register size. */
|
||||
tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
|
||||
/* Value sign-extended to tcg register size. */
|
||||
tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
|
||||
void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
|
||||
/* Temporary aliases until backends are converted. */
|
||||
#ifdef TARGET_WORDS_BIGENDIAN
|
||||
|
|
@ -1357,30 +1357,30 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
|
|||
|
||||
uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
|
||||
uint32_t cmpv, uint32_t newv,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
uint32_t cpu_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr,
|
||||
uint32_t cmpv, uint32_t newv,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
uint32_t cpu_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr,
|
||||
uint32_t cmpv, uint32_t newv,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
uint64_t cpu_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr,
|
||||
uint64_t cmpv, uint64_t newv,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
uint32_t cpu_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr,
|
||||
uint32_t cmpv, uint32_t newv,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
uint32_t cpu_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr,
|
||||
uint32_t cmpv, uint32_t newv,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
uint64_t cpu_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr,
|
||||
uint64_t cmpv, uint64_t newv,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
|
||||
#define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \
|
||||
TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu \
|
||||
(CPUArchState *env, target_ulong addr, TYPE val, \
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
|
||||
#ifdef CONFIG_ATOMIC64
|
||||
#define GEN_ATOMIC_HELPER_ALL(NAME) \
|
||||
|
|
@ -1427,19 +1427,19 @@ GEN_ATOMIC_HELPER_ALL(xchg)
|
|||
|
||||
Int128 cpu_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr,
|
||||
Int128 cmpv, Int128 newv,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr,
|
||||
Int128 cmpv, Int128 newv,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
|
||||
Int128 cpu_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
Int128 cpu_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
void cpu_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
void cpu_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
MemOpIdx oi, uintptr_t retaddr);
|
||||
|
||||
#ifdef CONFIG_DEBUG_TCG
|
||||
void tcg_assert_listed_vecop(TCGOpcode);
|
||||
|
|
|
|||
|
|
@ -531,8 +531,8 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
|
|||
clear_helper_retaddr();
|
||||
#else
|
||||
int mem_idx = cpu_mmu_index(env, false);
|
||||
TCGMemOpIdx oi0 = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
|
||||
TCGMemOpIdx oi1 = make_memop_idx(MO_LEQ, mem_idx);
|
||||
MemOpIdx oi0 = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
|
||||
MemOpIdx oi1 = make_memop_idx(MO_LEQ, mem_idx);
|
||||
|
||||
o0 = helper_le_ldq_mmu(env, addr + 0, oi0, ra);
|
||||
o1 = helper_le_ldq_mmu(env, addr + 8, oi1, ra);
|
||||
|
|
@ -555,7 +555,7 @@ uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t addr,
|
|||
uintptr_t ra = GETPC();
|
||||
bool success;
|
||||
int mem_idx;
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
|
||||
assert(HAVE_CMPXCHG128);
|
||||
|
||||
|
|
@ -601,8 +601,8 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr,
|
|||
clear_helper_retaddr();
|
||||
#else
|
||||
int mem_idx = cpu_mmu_index(env, false);
|
||||
TCGMemOpIdx oi0 = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
|
||||
TCGMemOpIdx oi1 = make_memop_idx(MO_BEQ, mem_idx);
|
||||
MemOpIdx oi0 = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
|
||||
MemOpIdx oi1 = make_memop_idx(MO_BEQ, mem_idx);
|
||||
|
||||
o1 = helper_be_ldq_mmu(env, addr + 0, oi0, ra);
|
||||
o0 = helper_be_ldq_mmu(env, addr + 8, oi1, ra);
|
||||
|
|
@ -625,7 +625,7 @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t addr,
|
|||
uintptr_t ra = GETPC();
|
||||
bool success;
|
||||
int mem_idx;
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
|
||||
assert(HAVE_CMPXCHG128);
|
||||
|
||||
|
|
@ -651,7 +651,7 @@ void HELPER(casp_le_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
|
|||
Int128 oldv, cmpv, newv;
|
||||
uintptr_t ra = GETPC();
|
||||
int mem_idx;
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
|
||||
assert(HAVE_CMPXCHG128);
|
||||
|
||||
|
|
@ -672,7 +672,7 @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
|
|||
Int128 oldv, cmpv, newv;
|
||||
uintptr_t ra = GETPC();
|
||||
int mem_idx;
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
|
||||
assert(HAVE_CMPXCHG128);
|
||||
|
||||
|
|
|
|||
|
|
@ -1930,7 +1930,7 @@ static bool do_v7m_function_return(ARMCPU *cpu)
|
|||
|
||||
{
|
||||
bool threadmode, spsel;
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
ARMMMUIdx mmu_idx;
|
||||
uint32_t *frame_sp_p;
|
||||
uint32_t frameptr;
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ void helper_cmpxchg8b(CPUX86State *env, target_ulong a0)
|
|||
{
|
||||
uintptr_t ra = GETPC();
|
||||
int mem_idx = cpu_mmu_index(env, false);
|
||||
TCGMemOpIdx oi = make_memop_idx(MO_TEQ, mem_idx);
|
||||
MemOpIdx oi = make_memop_idx(MO_TEQ, mem_idx);
|
||||
oldv = cpu_atomic_cmpxchgq_le_mmu(env, a0, cmpv, newv, oi, ra);
|
||||
}
|
||||
|
||||
|
|
@ -136,7 +136,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a0)
|
|||
Int128 newv = int128_make128(env->regs[R_EBX], env->regs[R_ECX]);
|
||||
|
||||
int mem_idx = cpu_mmu_index(env, false);
|
||||
TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
|
||||
MemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
|
||||
Int128 oldv = cpu_atomic_cmpxchgo_le_mmu(env, a0, cmpv, newv, oi, ra);
|
||||
|
||||
if (int128_eq(oldv, cmpv)) {
|
||||
|
|
|
|||
|
|
@ -775,7 +775,7 @@ static void do_cas2l(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2,
|
|||
uintptr_t ra = GETPC();
|
||||
#if defined(CONFIG_ATOMIC64)
|
||||
int mmu_idx = cpu_mmu_index(env, 0);
|
||||
TCGMemOpIdx oi = make_memop_idx(MO_BEQ, mmu_idx);
|
||||
MemOpIdx oi = make_memop_idx(MO_BEQ, mmu_idx);
|
||||
#endif
|
||||
|
||||
if (parallel) {
|
||||
|
|
|
|||
|
|
@ -8211,9 +8211,9 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
|||
#define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
#define MEMOP_IDX(DF) \
|
||||
TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
|
||||
cpu_mmu_index(env, false));
|
||||
#define MEMOP_IDX(DF) \
|
||||
MemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
|
||||
cpu_mmu_index(env, false));
|
||||
#else
|
||||
#define MEMOP_IDX(DF)
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -239,7 +239,7 @@ static void do_access_memset(CPUS390XState *env, vaddr vaddr, char *haddr,
|
|||
g_assert(haddr);
|
||||
memset(haddr, byte, size);
|
||||
#else
|
||||
TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
|
||||
MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
|
||||
int i;
|
||||
|
||||
if (likely(haddr)) {
|
||||
|
|
@ -282,7 +282,7 @@ static uint8_t do_access_get_byte(CPUS390XState *env, vaddr vaddr, char **haddr,
|
|||
#ifdef CONFIG_USER_ONLY
|
||||
return ldub_p(*haddr + offset);
|
||||
#else
|
||||
TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
|
||||
MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
|
||||
uint8_t byte;
|
||||
|
||||
if (likely(*haddr)) {
|
||||
|
|
@ -316,7 +316,7 @@ static void do_access_set_byte(CPUS390XState *env, vaddr vaddr, char **haddr,
|
|||
#ifdef CONFIG_USER_ONLY
|
||||
stb_p(*haddr + offset, byte);
|
||||
#else
|
||||
TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
|
||||
MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
|
||||
|
||||
if (likely(*haddr)) {
|
||||
stb_p(*haddr + offset, byte);
|
||||
|
|
@ -1804,7 +1804,7 @@ void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr,
|
|||
Int128 cmpv = int128_make128(env->regs[r1 + 1], env->regs[r1]);
|
||||
Int128 newv = int128_make128(env->regs[r3 + 1], env->regs[r3]);
|
||||
int mem_idx;
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
Int128 oldv;
|
||||
bool fail;
|
||||
|
||||
|
|
@ -1884,7 +1884,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1,
|
|||
uint32_t *haddr = g2h(env_cpu(env), a1);
|
||||
ov = qatomic_cmpxchg__nocheck(haddr, cv, nv);
|
||||
#else
|
||||
TCGMemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mem_idx);
|
||||
MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mem_idx);
|
||||
ov = cpu_atomic_cmpxchgl_be_mmu(env, a1, cv, nv, oi, ra);
|
||||
#endif
|
||||
} else {
|
||||
|
|
@ -1904,7 +1904,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1,
|
|||
|
||||
if (parallel) {
|
||||
#ifdef CONFIG_ATOMIC64
|
||||
TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN, mem_idx);
|
||||
MemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN, mem_idx);
|
||||
ov = cpu_atomic_cmpxchgq_be_mmu(env, a1, cv, nv, oi, ra);
|
||||
#else
|
||||
/* Note that we asserted !parallel above. */
|
||||
|
|
@ -1940,7 +1940,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1,
|
|||
cpu_stq_data_ra(env, a1 + 0, int128_gethi(nv), ra);
|
||||
cpu_stq_data_ra(env, a1 + 8, int128_getlo(nv), ra);
|
||||
} else if (HAVE_CMPXCHG128) {
|
||||
TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
|
||||
MemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
|
||||
ov = cpu_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, ra);
|
||||
cc = !int128_eq(ov, cv);
|
||||
} else {
|
||||
|
|
@ -1979,7 +1979,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1,
|
|||
cpu_stq_data_ra(env, a2 + 0, svh, ra);
|
||||
cpu_stq_data_ra(env, a2 + 8, svl, ra);
|
||||
} else if (HAVE_ATOMIC128) {
|
||||
TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
|
||||
MemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
|
||||
Int128 sv = int128_make128(svl, svh);
|
||||
cpu_atomic_sto_be_mmu(env, a2, sv, oi, ra);
|
||||
} else {
|
||||
|
|
@ -2497,7 +2497,7 @@ uint64_t HELPER(lpq_parallel)(CPUS390XState *env, uint64_t addr)
|
|||
uintptr_t ra = GETPC();
|
||||
uint64_t hi, lo;
|
||||
int mem_idx;
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
Int128 v;
|
||||
|
||||
assert(HAVE_ATOMIC128);
|
||||
|
|
@ -2528,7 +2528,7 @@ void HELPER(stpq_parallel)(CPUS390XState *env, uint64_t addr,
|
|||
{
|
||||
uintptr_t ra = GETPC();
|
||||
int mem_idx;
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
Int128 v;
|
||||
|
||||
assert(HAVE_ATOMIC128);
|
||||
|
|
|
|||
|
|
@ -1318,7 +1318,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
|
|||
case ASI_SNF:
|
||||
case ASI_SNFL:
|
||||
{
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
int idx = (env->pstate & PS_PRIV
|
||||
? (asi & 1 ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX)
|
||||
: (asi & 1 ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX));
|
||||
|
|
|
|||
|
|
@ -1545,7 +1545,7 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, TCGReg d,
|
|||
#include "../tcg-ldst.c.inc"
|
||||
|
||||
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
|
||||
* TCGMemOpIdx oi, uintptr_t ra)
|
||||
* MemOpIdx oi, uintptr_t ra)
|
||||
*/
|
||||
static void * const qemu_ld_helpers[MO_SIZE + 1] = {
|
||||
[MO_8] = helper_ret_ldub_mmu,
|
||||
|
|
@ -1561,7 +1561,7 @@ static void * const qemu_ld_helpers[MO_SIZE + 1] = {
|
|||
};
|
||||
|
||||
/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
|
||||
* uintxx_t val, TCGMemOpIdx oi,
|
||||
* uintxx_t val, MemOpIdx oi,
|
||||
* uintptr_t ra)
|
||||
*/
|
||||
static void * const qemu_st_helpers[MO_SIZE + 1] = {
|
||||
|
|
@ -1586,7 +1586,7 @@ static inline void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target)
|
|||
|
||||
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
|
||||
{
|
||||
TCGMemOpIdx oi = lb->oi;
|
||||
MemOpIdx oi = lb->oi;
|
||||
MemOp opc = get_memop(oi);
|
||||
MemOp size = opc & MO_SIZE;
|
||||
|
||||
|
|
@ -1611,7 +1611,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
|
|||
|
||||
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
|
||||
{
|
||||
TCGMemOpIdx oi = lb->oi;
|
||||
MemOpIdx oi = lb->oi;
|
||||
MemOp opc = get_memop(oi);
|
||||
MemOp size = opc & MO_SIZE;
|
||||
|
||||
|
|
@ -1629,7 +1629,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
|
|||
return true;
|
||||
}
|
||||
|
||||
static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
|
||||
static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
|
||||
TCGType ext, TCGReg data_reg, TCGReg addr_reg,
|
||||
tcg_insn_unit *raddr, tcg_insn_unit *label_ptr)
|
||||
{
|
||||
|
|
@ -1778,7 +1778,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,
|
|||
}
|
||||
|
||||
static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
|
||||
TCGMemOpIdx oi, TCGType ext)
|
||||
MemOpIdx oi, TCGType ext)
|
||||
{
|
||||
MemOp memop = get_memop(oi);
|
||||
const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
|
||||
|
|
@ -1803,7 +1803,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
|
|||
}
|
||||
|
||||
static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
|
||||
TCGMemOpIdx oi)
|
||||
MemOpIdx oi)
|
||||
{
|
||||
MemOp memop = get_memop(oi);
|
||||
const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
|
||||
|
|
|
|||
|
|
@ -1632,7 +1632,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
|
|||
/* Record the context of a call to the out of line helper code for the slow
|
||||
path for a load or store, so that we can later generate the correct
|
||||
helper code. */
|
||||
static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
|
||||
static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
|
||||
TCGReg datalo, TCGReg datahi, TCGReg addrlo,
|
||||
TCGReg addrhi, tcg_insn_unit *raddr,
|
||||
tcg_insn_unit *label_ptr)
|
||||
|
|
@ -1652,7 +1652,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
|
|||
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
|
||||
{
|
||||
TCGReg argreg, datalo, datahi;
|
||||
TCGMemOpIdx oi = lb->oi;
|
||||
MemOpIdx oi = lb->oi;
|
||||
MemOp opc = get_memop(oi);
|
||||
void *func;
|
||||
|
||||
|
|
@ -1716,7 +1716,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
|
|||
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
|
||||
{
|
||||
TCGReg argreg, datalo, datahi;
|
||||
TCGMemOpIdx oi = lb->oi;
|
||||
MemOpIdx oi = lb->oi;
|
||||
MemOp opc = get_memop(oi);
|
||||
|
||||
if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
|
||||
|
|
@ -1846,7 +1846,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo,
|
|||
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
|
||||
{
|
||||
TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
MemOp opc;
|
||||
#ifdef CONFIG_SOFTMMU
|
||||
int mem_index;
|
||||
|
|
@ -1952,7 +1952,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo,
|
|||
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
|
||||
{
|
||||
TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
MemOp opc;
|
||||
#ifdef CONFIG_SOFTMMU
|
||||
int mem_index;
|
||||
|
|
|
|||
|
|
@ -1741,7 +1741,7 @@ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
|
|||
* for a load or store, so that we can later generate the correct helper code
|
||||
*/
|
||||
static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64,
|
||||
TCGMemOpIdx oi,
|
||||
MemOpIdx oi,
|
||||
TCGReg datalo, TCGReg datahi,
|
||||
TCGReg addrlo, TCGReg addrhi,
|
||||
tcg_insn_unit *raddr,
|
||||
|
|
@ -1768,7 +1768,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64,
|
|||
*/
|
||||
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
|
||||
{
|
||||
TCGMemOpIdx oi = l->oi;
|
||||
MemOpIdx oi = l->oi;
|
||||
MemOp opc = get_memop(oi);
|
||||
TCGReg data_reg;
|
||||
tcg_insn_unit **label_ptr = &l->label_ptr[0];
|
||||
|
|
@ -1853,7 +1853,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
|
|||
*/
|
||||
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
|
||||
{
|
||||
TCGMemOpIdx oi = l->oi;
|
||||
MemOpIdx oi = l->oi;
|
||||
MemOp opc = get_memop(oi);
|
||||
MemOp s_bits = opc & MO_SIZE;
|
||||
tcg_insn_unit **label_ptr = &l->label_ptr[0];
|
||||
|
|
@ -2054,7 +2054,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
|
|||
{
|
||||
TCGReg datalo, datahi, addrlo;
|
||||
TCGReg addrhi __attribute__((unused));
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
MemOp opc;
|
||||
#if defined(CONFIG_SOFTMMU)
|
||||
int mem_index;
|
||||
|
|
@ -2143,7 +2143,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
|
|||
{
|
||||
TCGReg datalo, datahi, addrlo;
|
||||
TCGReg addrhi __attribute__((unused));
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
MemOp opc;
|
||||
#if defined(CONFIG_SOFTMMU)
|
||||
int mem_index;
|
||||
|
|
|
|||
|
|
@ -1120,7 +1120,7 @@ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
|
|||
* Clobbers TMP0, TMP1, TMP2, TMP3.
|
||||
*/
|
||||
static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
|
||||
TCGReg addrh, TCGMemOpIdx oi,
|
||||
TCGReg addrh, MemOpIdx oi,
|
||||
tcg_insn_unit *label_ptr[2], bool is_load)
|
||||
{
|
||||
MemOp opc = get_memop(oi);
|
||||
|
|
@ -1196,7 +1196,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
|
|||
tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl);
|
||||
}
|
||||
|
||||
static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
|
||||
static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi,
|
||||
TCGType ext,
|
||||
TCGReg datalo, TCGReg datahi,
|
||||
TCGReg addrlo, TCGReg addrhi,
|
||||
|
|
@ -1221,7 +1221,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
|
|||
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
|
||||
{
|
||||
const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
|
||||
TCGMemOpIdx oi = l->oi;
|
||||
MemOpIdx oi = l->oi;
|
||||
MemOp opc = get_memop(oi);
|
||||
TCGReg v0;
|
||||
int i;
|
||||
|
|
@ -1275,7 +1275,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
|
|||
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
|
||||
{
|
||||
const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
|
||||
TCGMemOpIdx oi = l->oi;
|
||||
MemOpIdx oi = l->oi;
|
||||
MemOp opc = get_memop(oi);
|
||||
MemOp s_bits = opc & MO_SIZE;
|
||||
int i;
|
||||
|
|
@ -1434,7 +1434,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
|
|||
{
|
||||
TCGReg addr_regl, addr_regh __attribute__((unused));
|
||||
TCGReg data_regl, data_regh;
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
MemOp opc;
|
||||
#if defined(CONFIG_SOFTMMU)
|
||||
tcg_insn_unit *label_ptr[2];
|
||||
|
|
@ -1536,7 +1536,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
|
|||
{
|
||||
TCGReg addr_regl, addr_regh __attribute__((unused));
|
||||
TCGReg data_regl, data_regh;
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
MemOp opc;
|
||||
#if defined(CONFIG_SOFTMMU)
|
||||
tcg_insn_unit *label_ptr[2];
|
||||
|
|
|
|||
|
|
@ -1023,7 +1023,7 @@ void tcg_optimize(TCGContext *s)
|
|||
|
||||
CASE_OP_32_64(qemu_ld):
|
||||
{
|
||||
TCGMemOpIdx oi = op->args[nb_oargs + nb_iargs];
|
||||
MemOpIdx oi = op->args[nb_oargs + nb_iargs];
|
||||
MemOp mop = get_memop(oi);
|
||||
if (!(mop & MO_SIGN)) {
|
||||
mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
|
||||
|
|
|
|||
|
|
@ -2103,7 +2103,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc,
|
|||
/* Record the context of a call to the out of line helper code for the slow
|
||||
path for a load or store, so that we can later generate the correct
|
||||
helper code. */
|
||||
static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
|
||||
static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
|
||||
TCGReg datalo_reg, TCGReg datahi_reg,
|
||||
TCGReg addrlo_reg, TCGReg addrhi_reg,
|
||||
tcg_insn_unit *raddr, tcg_insn_unit *lptr)
|
||||
|
|
@ -2122,7 +2122,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
|
|||
|
||||
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
|
||||
{
|
||||
TCGMemOpIdx oi = lb->oi;
|
||||
MemOpIdx oi = lb->oi;
|
||||
MemOp opc = get_memop(oi);
|
||||
TCGReg hi, lo, arg = TCG_REG_R3;
|
||||
|
||||
|
|
@ -2169,7 +2169,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
|
|||
|
||||
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
|
||||
{
|
||||
TCGMemOpIdx oi = lb->oi;
|
||||
MemOpIdx oi = lb->oi;
|
||||
MemOp opc = get_memop(oi);
|
||||
MemOp s_bits = opc & MO_SIZE;
|
||||
TCGReg hi, lo, arg = TCG_REG_R3;
|
||||
|
|
@ -2233,7 +2233,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
|
|||
{
|
||||
TCGReg datalo, datahi, addrlo, rbase;
|
||||
TCGReg addrhi __attribute__((unused));
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
MemOp opc, s_bits;
|
||||
#ifdef CONFIG_SOFTMMU
|
||||
int mem_index;
|
||||
|
|
@ -2308,7 +2308,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
|
|||
{
|
||||
TCGReg datalo, datahi, addrlo, rbase;
|
||||
TCGReg addrhi __attribute__((unused));
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
MemOp opc, s_bits;
|
||||
#ifdef CONFIG_SOFTMMU
|
||||
int mem_index;
|
||||
|
|
|
|||
|
|
@ -850,7 +850,7 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
|
|||
#include "../tcg-ldst.c.inc"
|
||||
|
||||
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
|
||||
* TCGMemOpIdx oi, uintptr_t ra)
|
||||
* MemOpIdx oi, uintptr_t ra)
|
||||
*/
|
||||
static void * const qemu_ld_helpers[MO_SSIZE + 1] = {
|
||||
[MO_UB] = helper_ret_ldub_mmu,
|
||||
|
|
@ -875,7 +875,7 @@ static void * const qemu_ld_helpers[MO_SSIZE + 1] = {
|
|||
};
|
||||
|
||||
/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
|
||||
* uintxx_t val, TCGMemOpIdx oi,
|
||||
* uintxx_t val, MemOpIdx oi,
|
||||
* uintptr_t ra)
|
||||
*/
|
||||
static void * const qemu_st_helpers[MO_SIZE + 1] = {
|
||||
|
|
@ -906,7 +906,7 @@ static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target)
|
|||
}
|
||||
|
||||
static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
|
||||
TCGReg addrh, TCGMemOpIdx oi,
|
||||
TCGReg addrh, MemOpIdx oi,
|
||||
tcg_insn_unit **label_ptr, bool is_load)
|
||||
{
|
||||
MemOp opc = get_memop(oi);
|
||||
|
|
@ -959,7 +959,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
|
|||
tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl);
|
||||
}
|
||||
|
||||
static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
|
||||
static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi,
|
||||
TCGType ext,
|
||||
TCGReg datalo, TCGReg datahi,
|
||||
TCGReg addrlo, TCGReg addrhi,
|
||||
|
|
@ -980,7 +980,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
|
|||
|
||||
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
|
||||
{
|
||||
TCGMemOpIdx oi = l->oi;
|
||||
MemOpIdx oi = l->oi;
|
||||
MemOp opc = get_memop(oi);
|
||||
TCGReg a0 = tcg_target_call_iarg_regs[0];
|
||||
TCGReg a1 = tcg_target_call_iarg_regs[1];
|
||||
|
|
@ -1012,7 +1012,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
|
|||
|
||||
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
|
||||
{
|
||||
TCGMemOpIdx oi = l->oi;
|
||||
MemOpIdx oi = l->oi;
|
||||
MemOp opc = get_memop(oi);
|
||||
MemOp s_bits = opc & MO_SIZE;
|
||||
TCGReg a0 = tcg_target_call_iarg_regs[0];
|
||||
|
|
@ -1104,7 +1104,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
|
|||
{
|
||||
TCGReg addr_regl, addr_regh __attribute__((unused));
|
||||
TCGReg data_regl, data_regh;
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
MemOp opc;
|
||||
#if defined(CONFIG_SOFTMMU)
|
||||
tcg_insn_unit *label_ptr[1];
|
||||
|
|
@ -1170,7 +1170,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
|
|||
{
|
||||
TCGReg addr_regl, addr_regh __attribute__((unused));
|
||||
TCGReg data_regl, data_regh;
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
MemOp opc;
|
||||
#if defined(CONFIG_SOFTMMU)
|
||||
tcg_insn_unit *label_ptr[1];
|
||||
|
|
|
|||
|
|
@ -1547,7 +1547,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc,
|
|||
return addr_reg;
|
||||
}
|
||||
|
||||
static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
|
||||
static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
|
||||
TCGReg data, TCGReg addr,
|
||||
tcg_insn_unit *raddr, tcg_insn_unit *label_ptr)
|
||||
{
|
||||
|
|
@ -1565,7 +1565,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
|
|||
{
|
||||
TCGReg addr_reg = lb->addrlo_reg;
|
||||
TCGReg data_reg = lb->datalo_reg;
|
||||
TCGMemOpIdx oi = lb->oi;
|
||||
MemOpIdx oi = lb->oi;
|
||||
MemOp opc = get_memop(oi);
|
||||
|
||||
if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
|
||||
|
|
@ -1590,7 +1590,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
|
|||
{
|
||||
TCGReg addr_reg = lb->addrlo_reg;
|
||||
TCGReg data_reg = lb->datalo_reg;
|
||||
TCGMemOpIdx oi = lb->oi;
|
||||
MemOpIdx oi = lb->oi;
|
||||
MemOp opc = get_memop(oi);
|
||||
|
||||
if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
|
||||
|
|
@ -1644,7 +1644,7 @@ static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,
|
|||
#endif /* CONFIG_SOFTMMU */
|
||||
|
||||
static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
|
||||
TCGMemOpIdx oi)
|
||||
MemOpIdx oi)
|
||||
{
|
||||
MemOp opc = get_memop(oi);
|
||||
#ifdef CONFIG_SOFTMMU
|
||||
|
|
@ -1671,7 +1671,7 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
|
|||
}
|
||||
|
||||
static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
|
||||
TCGMemOpIdx oi)
|
||||
MemOpIdx oi)
|
||||
{
|
||||
MemOp opc = get_memop(oi);
|
||||
#ifdef CONFIG_SOFTMMU
|
||||
|
|
|
|||
|
|
@ -1148,7 +1148,7 @@ static const int qemu_st_opc[(MO_SIZE | MO_BSWAP) + 1] = {
|
|||
};
|
||||
|
||||
static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
|
||||
TCGMemOpIdx oi, bool is_64)
|
||||
MemOpIdx oi, bool is_64)
|
||||
{
|
||||
MemOp memop = get_memop(oi);
|
||||
#ifdef CONFIG_SOFTMMU
|
||||
|
|
@ -1230,7 +1230,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
|
|||
}
|
||||
|
||||
static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,
|
||||
TCGMemOpIdx oi)
|
||||
MemOpIdx oi)
|
||||
{
|
||||
MemOp memop = get_memop(oi);
|
||||
#ifdef CONFIG_SOFTMMU
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
|
||||
typedef struct TCGLabelQemuLdst {
|
||||
bool is_ld; /* qemu_ld: true, qemu_st: false */
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
TCGType type; /* result type of a load */
|
||||
TCGReg addrlo_reg; /* reg index for low word of guest virtual addr */
|
||||
TCGReg addrhi_reg; /* reg index for high word of guest virtual addr */
|
||||
|
|
|
|||
12
tcg/tcg-op.c
12
tcg/tcg-op.c
|
|
@ -2797,7 +2797,7 @@ static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st)
|
|||
static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr,
|
||||
MemOp memop, TCGArg idx)
|
||||
{
|
||||
TCGMemOpIdx oi = make_memop_idx(memop, idx);
|
||||
MemOpIdx oi = make_memop_idx(memop, idx);
|
||||
#if TARGET_LONG_BITS == 32
|
||||
tcg_gen_op3i_i32(opc, val, addr, oi);
|
||||
#else
|
||||
|
|
@ -2812,7 +2812,7 @@ static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr,
|
|||
static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr,
|
||||
MemOp memop, TCGArg idx)
|
||||
{
|
||||
TCGMemOpIdx oi = make_memop_idx(memop, idx);
|
||||
MemOpIdx oi = make_memop_idx(memop, idx);
|
||||
#if TARGET_LONG_BITS == 32
|
||||
if (TCG_TARGET_REG_BITS == 32) {
|
||||
tcg_gen_op4i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), addr, oi);
|
||||
|
|
@ -3132,7 +3132,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv,
|
|||
tcg_temp_free_i32(t1);
|
||||
} else {
|
||||
gen_atomic_cx_i32 gen;
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
|
||||
gen = table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)];
|
||||
tcg_debug_assert(gen != NULL);
|
||||
|
|
@ -3171,7 +3171,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv,
|
|||
} else if ((memop & MO_SIZE) == MO_64) {
|
||||
#ifdef CONFIG_ATOMIC64
|
||||
gen_atomic_cx_i64 gen;
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
|
||||
gen = table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)];
|
||||
tcg_debug_assert(gen != NULL);
|
||||
|
|
@ -3227,7 +3227,7 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,
|
|||
TCGArg idx, MemOp memop, void * const table[])
|
||||
{
|
||||
gen_atomic_op_i32 gen;
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
|
||||
memop = tcg_canonicalize_memop(memop, 0, 0);
|
||||
|
||||
|
|
@ -3269,7 +3269,7 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,
|
|||
if ((memop & MO_SIZE) == MO_64) {
|
||||
#ifdef CONFIG_ATOMIC64
|
||||
gen_atomic_op_i64 gen;
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
|
||||
gen = table[memop & (MO_SIZE | MO_BSWAP)];
|
||||
tcg_debug_assert(gen != NULL);
|
||||
|
|
|
|||
|
|
@ -1910,7 +1910,7 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
|
|||
case INDEX_op_qemu_ld_i64:
|
||||
case INDEX_op_qemu_st_i64:
|
||||
{
|
||||
TCGMemOpIdx oi = op->args[k++];
|
||||
MemOpIdx oi = op->args[k++];
|
||||
MemOp op = get_memop(oi);
|
||||
unsigned ix = get_mmuidx(oi);
|
||||
|
||||
|
|
|
|||
14
tcg/tci.c
14
tcg/tci.c
|
|
@ -61,7 +61,7 @@ static uint64_t tci_uint64(uint32_t high, uint32_t low)
|
|||
* i = immediate (uint32_t)
|
||||
* I = immediate (tcg_target_ulong)
|
||||
* l = label or pointer
|
||||
* m = immediate (TCGMemOpIdx)
|
||||
* m = immediate (MemOpIdx)
|
||||
* n = immediate (call return length)
|
||||
* r = register
|
||||
* s = signed ldst offset
|
||||
|
|
@ -105,7 +105,7 @@ static void tci_args_ri(uint32_t insn, TCGReg *r0, tcg_target_ulong *i1)
|
|||
}
|
||||
|
||||
static void tci_args_rrm(uint32_t insn, TCGReg *r0,
|
||||
TCGReg *r1, TCGMemOpIdx *m2)
|
||||
TCGReg *r1, MemOpIdx *m2)
|
||||
{
|
||||
*r0 = extract32(insn, 8, 4);
|
||||
*r1 = extract32(insn, 12, 4);
|
||||
|
|
@ -145,7 +145,7 @@ static void tci_args_rrrc(uint32_t insn,
|
|||
}
|
||||
|
||||
static void tci_args_rrrm(uint32_t insn,
|
||||
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx *m3)
|
||||
TCGReg *r0, TCGReg *r1, TCGReg *r2, MemOpIdx *m3)
|
||||
{
|
||||
*r0 = extract32(insn, 8, 4);
|
||||
*r1 = extract32(insn, 12, 4);
|
||||
|
|
@ -289,7 +289,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
|
|||
}
|
||||
|
||||
static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
|
||||
TCGMemOpIdx oi, const void *tb_ptr)
|
||||
MemOpIdx oi, const void *tb_ptr)
|
||||
{
|
||||
MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE);
|
||||
uintptr_t ra = (uintptr_t)tb_ptr;
|
||||
|
|
@ -374,7 +374,7 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
|
|||
}
|
||||
|
||||
static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val,
|
||||
TCGMemOpIdx oi, const void *tb_ptr)
|
||||
MemOpIdx oi, const void *tb_ptr)
|
||||
{
|
||||
MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE);
|
||||
uintptr_t ra = (uintptr_t)tb_ptr;
|
||||
|
|
@ -482,7 +482,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
|
|||
uint32_t tmp32;
|
||||
uint64_t tmp64;
|
||||
uint64_t T1, T2;
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
int32_t ofs;
|
||||
void *ptr;
|
||||
|
||||
|
|
@ -1148,7 +1148,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
|
|||
tcg_target_ulong i1;
|
||||
int32_t s2;
|
||||
TCGCond c;
|
||||
TCGMemOpIdx oi;
|
||||
MemOpIdx oi;
|
||||
uint8_t pos, len;
|
||||
void *ptr;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue