From 6abcec36741e589c855084e59195fc3454bf4be6 Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Sun, 7 Mar 2021 22:25:52 +0100 Subject: [PATCH 1/4] target/m68k: implement rtr instruction This is needed to boot MacOS ROM. Pull the condition code and the program counter from the stack. Operation: (SP) -> CCR SP + 2 -> SP (SP) -> PC SP + 4 -> SP This operation is not privileged. Reported-by: Mark Cave-Ayland Tested-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <20210307212552.523552-1-laurent@vivier.eu> --- target/m68k/translate.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index ac936ebe8f..200018ae6a 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -2969,6 +2969,25 @@ DISAS_INSN(rtd) gen_jmp(s, tmp); } +DISAS_INSN(rtr) +{ + TCGv tmp; + TCGv ccr; + TCGv sp; + + sp = tcg_temp_new(); + ccr = gen_load(s, OS_WORD, QREG_SP, 0, IS_USER(s)); + tcg_gen_addi_i32(sp, QREG_SP, 2); + tmp = gen_load(s, OS_LONG, sp, 0, IS_USER(s)); + tcg_gen_addi_i32(QREG_SP, sp, 4); + tcg_temp_free(sp); + + gen_set_sr(s, ccr, true); + tcg_temp_free(ccr); + + gen_jmp(s, tmp); +} + DISAS_INSN(rts) { TCGv tmp; @@ -6015,6 +6034,7 @@ void register_m68k_insns (CPUM68KState *env) BASE(nop, 4e71, ffff); INSN(rtd, 4e74, ffff, RTD); BASE(rts, 4e75, ffff); + INSN(rtr, 4e77, ffff, M68000); BASE(jump, 4e80, ffc0); BASE(jump, 4ec0, ffc0); INSN(addsubq, 5000, f080, M68000); From d6cbd8f7a19e6f0fd22a598aad992c4913f481f2 Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Mon, 8 Mar 2021 12:11:53 +0000 Subject: [PATCH 2/4] target/m68k: don't set SSW ATC bit for physical bus errors If a NuBus slot doesn't contain a card, the Quadra hardware generates a physical bus error if the CPU attempts to access the slot address space. Both Linux and MacOS use a separate bus error handler during NuBus accesses in order to detect and recover when addressing empty slots. According to the MC68040 users manual the ATC bit of the SSW is used to distinguish between ATC faults and physical bus errors. MacOS specifically checks the stack frame generated by a NuBus error and panics if the SSW ATC bit is set. Update m68k_cpu_transaction_failed() so that the SSW ATC bit is not set if the memory API returns MEMTX_DECODE_ERROR which will be used to indicate that an access to an empty NuBus slot occurred. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20210308121155.2476-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- target/m68k/op_helper.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 730cdf7744..5f981e5bf6 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -468,7 +468,17 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, if (m68k_feature(env, M68K_FEATURE_M68040)) { env->mmu.mmusr = 0; - env->mmu.ssw |= M68K_ATC_040; + + /* + * According to the MC68040 users manual the ATC bit of the SSW is + * used to distinguish between ATC faults and physical bus errors. + * In the case of a bus error e.g. during nubus read from an empty + * slot this bit should not be set + */ + if (response != MEMTX_DECODE_ERROR) { + env->mmu.ssw |= M68K_ATC_040; + } + /* FIXME: manage MMU table access error */ env->mmu.ssw &= ~M68K_TM_040; if (env->sr & SR_S) { /* SUPERVISOR */ From 469949c90252d80693aa70652d8251d1d602557e Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Mon, 8 Mar 2021 12:11:54 +0000 Subject: [PATCH 3/4] target/m68k: reformat m68k_features enum Move the feature comment from after the feature name to the preceding line to allow for longer feature names and descriptions without hitting the 80 character line limit. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <20210308121155.2476-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- target/m68k/cpu.h | 66 +++++++++++++++++++++++++++++++---------------- 1 file changed, 44 insertions(+), 22 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 7c3feeaf8a..ce558e9b03 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -475,36 +475,58 @@ void do_m68k_semihosting(CPUM68KState *env, int nr); */ enum m68k_features { - M68K_FEATURE_M68000, /* Base m68k instruction set */ + /* Base m68k instruction set */ + M68K_FEATURE_M68000, M68K_FEATURE_M68010, M68K_FEATURE_M68020, M68K_FEATURE_M68030, M68K_FEATURE_M68040, M68K_FEATURE_M68060, - M68K_FEATURE_CF_ISA_A, /* Base Coldfire set Rev A. */ - M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */ - M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ - M68K_FEATURE_BRAL, /* BRA with Long branch. (680[2346]0, ISA A+ or B). */ + /* Base Coldfire set Rev A. */ + M68K_FEATURE_CF_ISA_A, + /* (ISA B or C). */ + M68K_FEATURE_CF_ISA_B, + /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ + M68K_FEATURE_CF_ISA_APLUSC, + /* BRA with Long branch. (680[2346]0, ISA A+ or B). */ + M68K_FEATURE_BRAL, M68K_FEATURE_CF_FPU, M68K_FEATURE_CF_MAC, M68K_FEATURE_CF_EMAC, - M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */ - M68K_FEATURE_USP, /* User Stack Pointer. (680[012346]0, ISA A+, B or C).*/ - M68K_FEATURE_MSP, /* Master Stack Pointer. (680[234]0) */ - M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */ - M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */ - M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */ - M68K_FEATURE_LONG_MULDIV, /* 32 bit mul/div. (680[2346]0, and CPU32) */ - M68K_FEATURE_QUAD_MULDIV, /* 64 bit mul/div. (680[2346]0, and CPU32) */ - M68K_FEATURE_BCCL, /* Bcc with Long branches. (680[2346]0, and CPU32) */ - M68K_FEATURE_BITFIELD, /* BFxxx Bit field insns. (680[2346]0) */ - M68K_FEATURE_FPU, /* fpu insn. (680[46]0) */ - M68K_FEATURE_CAS, /* CAS/CAS2[WL] insns. (680[2346]0) */ - M68K_FEATURE_BKPT, /* BKPT insn. (680[12346]0, and CPU32) */ - M68K_FEATURE_RTD, /* RTD insn. (680[12346]0, and CPU32) */ - M68K_FEATURE_CHK2, /* CHK2 insn. (680[2346]0, and CPU32) */ - M68K_FEATURE_MOVEP, /* MOVEP insn. (680[01234]0, and CPU32) */ - M68K_FEATURE_MOVEC, /* MOVEC insn. (from 68010) */ + /* Revision B EMAC (dual accumulate). */ + M68K_FEATURE_CF_EMAC_B, + /* User Stack Pointer. (680[012346]0, ISA A+, B or C). */ + M68K_FEATURE_USP, + /* Master Stack Pointer. (680[234]0) */ + M68K_FEATURE_MSP, + /* 68020+ full extension word. */ + M68K_FEATURE_EXT_FULL, + /* word sized address index registers. */ + M68K_FEATURE_WORD_INDEX, + /* scaled address index registers. */ + M68K_FEATURE_SCALED_INDEX, + /* 32 bit mul/div. (680[2346]0, and CPU32) */ + M68K_FEATURE_LONG_MULDIV, + /* 64 bit mul/div. (680[2346]0, and CPU32) */ + M68K_FEATURE_QUAD_MULDIV, + /* Bcc with Long branches. (680[2346]0, and CPU32) */ + M68K_FEATURE_BCCL, + /* BFxxx Bit field insns. (680[2346]0) */ + M68K_FEATURE_BITFIELD, + /* fpu insn. (680[46]0) */ + M68K_FEATURE_FPU, + /* CAS/CAS2[WL] insns. (680[2346]0) */ + M68K_FEATURE_CAS, + /* BKPT insn. (680[12346]0, and CPU32) */ + M68K_FEATURE_BKPT, + /* RTD insn. (680[12346]0, and CPU32) */ + M68K_FEATURE_RTD, + /* CHK2 insn. (680[2346]0, and CPU32) */ + M68K_FEATURE_CHK2, + /* MOVEP insn. (680[01234]0, and CPU32) */ + M68K_FEATURE_MOVEP, + /* MOVEC insn. (from 68010) */ + M68K_FEATURE_MOVEC, }; static inline int m68k_feature(CPUM68KState *env, int feature) From a9431a03f70c8c711a870d4c1a0439bdbb4703cf Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Mon, 8 Mar 2021 12:11:55 +0000 Subject: [PATCH 4/4] target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature According to the M68040UM Appendix D the requirement for data accesses to be word aligned is only for the 68000, 68008 and 68010 CPUs. Later CPUs from the 68020 onwards will allow unaligned data accesses but at the cost of being less efficient. Add a new M68K_FEATURE_UNALIGNED_DATA feature to specify that data accesses are not required to be word aligned, and don't perform the alignment on the stack pointer when taking an exception if this feature is not selected. This is required because the MacOS DAFB driver attempts to call an A-trap with a byte-aligned stack pointer during initialisation and without this the stack pointer is off by one when the A-trap returns. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <20210308121155.2476-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- target/m68k/cpu.c | 1 + target/m68k/cpu.h | 2 ++ target/m68k/op_helper.c | 5 ++++- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 37d2ed9dc7..a14874b4da 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -161,6 +161,7 @@ static void m68020_cpu_initfn(Object *obj) m68k_set_feature(env, M68K_FEATURE_CAS); m68k_set_feature(env, M68K_FEATURE_CHK2); m68k_set_feature(env, M68K_FEATURE_MSP); + m68k_set_feature(env, M68K_FEATURE_UNALIGNED_DATA); } /* diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index ce558e9b03..402c86c876 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -527,6 +527,8 @@ enum m68k_features { M68K_FEATURE_MOVEP, /* MOVEC insn. (from 68010) */ M68K_FEATURE_MOVEC, + /* Unaligned data accesses (680[2346]0) */ + M68K_FEATURE_UNALIGNED_DATA, }; static inline int m68k_feature(CPUM68KState *env, int feature) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 5f981e5bf6..46ff81acc9 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -348,7 +348,10 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) cpu_m68k_set_sr(env, sr); sp = env->aregs[7]; - sp &= ~1; + if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) { + sp &= ~1; + } + if (cs->exception_index == EXCP_ACCESS) { if (env->mmu.fault) { cpu_abort(cs, "DOUBLE MMU FAULT\n");