From 24261de4916596d8ab5f5fee67e9e7a19e8325a5 Mon Sep 17 00:00:00 2001 From: Liu Jingqi Date: Tue, 6 Nov 2018 15:13:26 +0800 Subject: [PATCH 1/4] x86/cpu: Enable MOVDIRI cpu feature MOVDIRI moves doubleword or quadword from register to memory through direct store which is implemented by using write combining (WC) for writing data directly into memory without caching the data. The bit definition: CPUID.(EAX=7,ECX=0):ECX[bit 27] MOVDIRI The release document ref below link: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Cc: Xu Tao Signed-off-by: Liu Jingqi Message-Id: <1541488407-17045-2-git-send-email-jingqi.liu@intel.com> Signed-off-by: Eduardo Habkost --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f81d35e1f9..227baea337 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1023,7 +1023,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, "la57", NULL, NULL, NULL, NULL, NULL, "rdpid", NULL, - NULL, "cldemote", NULL, NULL, + NULL, "cldemote", NULL, "movdiri", NULL, NULL, NULL, NULL, }, .cpuid = { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9c52d0cbeb..b4f03ffd74 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -687,6 +687,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_ECX_LA57 (1U << 16) #define CPUID_7_0_ECX_RDPID (1U << 22) #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) /* CLDEMOTE Instruction */ +#define CPUID_7_0_ECX_MOVDIRI (1U << 27) /* MOVDIRI Instruction */ #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ From 1c65775ffc2dbd276a8bffe592feba0e186a151c Mon Sep 17 00:00:00 2001 From: Liu Jingqi Date: Tue, 6 Nov 2018 15:13:27 +0800 Subject: [PATCH 2/4] x86/cpu: Enable MOVDIR64B cpu feature MOVDIR64B moves 64-bytes as direct-store with 64-bytes write atomicity. Direct store is implemented by using write combining (WC) for writing data directly into memory without caching the data. The bit definition: CPUID.(EAX=7,ECX=0):ECX[bit 28] MOVDIR64B The release document ref below link: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Cc: Xu Tao Signed-off-by: Liu Jingqi Message-Id: <1541488407-17045-3-git-send-email-jingqi.liu@intel.com> Signed-off-by: Eduardo Habkost --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 227baea337..86a934d450 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1024,7 +1024,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "la57", NULL, NULL, NULL, NULL, NULL, "rdpid", NULL, NULL, "cldemote", NULL, "movdiri", - NULL, NULL, NULL, NULL, + "movdir64b", NULL, NULL, NULL, }, .cpuid = { .eax = 7, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index b4f03ffd74..ef41a033c5 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -688,6 +688,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_ECX_RDPID (1U << 22) #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) /* CLDEMOTE Instruction */ #define CPUID_7_0_ECX_MOVDIRI (1U << 27) /* MOVDIRI Instruction */ +#define CPUID_7_0_ECX_MOVDIR64B (1U << 28) /* MOVDIR64B Instruction */ #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ From 9115bb121323290a2fc3fc30fb35e0deee38d064 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 10 Dec 2018 11:46:54 +0000 Subject: [PATCH 3/4] target/i386/kvm.c: Don't mark cpuid_data as QEMU_PACKED MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit clang complains about taking the address of a packed member of a struct: target/i386/kvm.c:1245:27: warning: taking address of packed member 'cpuid' of class or structure '' may result in an unaligned pointer value [-Waddress-of-packed-member] c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0); ^~~~~~~~~~~~~~~~ target/i386/kvm.c:1297:31: warning: taking address of packed member 'cpuid' of class or structure '' may result in an unaligned pointer value [-Waddress-of-packed-member] c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0); ^~~~~~~~~~~~~~~~ The kernel's definitions of struct kvm_cpuid2 and struct kvm_cpuid_entry2 are carefully set up with padding fields so that there is no between-struct padding anyway, so the QEMU_PACKED annotation is unnecessary and might result in the compiler generating worse code. Drop it, and instead assert at build time that there is no stray padding. Signed-off-by: Peter Maydell Message-Id: <20181210114654.31433-1-peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Eduardo Habkost --- target/i386/kvm.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/i386/kvm.c b/target/i386/kvm.c index b2401d13ea..739cf8c8ea 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -864,7 +864,15 @@ int kvm_arch_init_vcpu(CPUState *cs) struct { struct kvm_cpuid2 cpuid; struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES]; - } QEMU_PACKED cpuid_data; + } cpuid_data; + /* + * The kernel defines these structs with padding fields so there + * should be no extra padding in our cpuid_data struct. + */ + QEMU_BUILD_BUG_ON(sizeof(cpuid_data) != + sizeof(struct kvm_cpuid2) + + sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES); + X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; uint32_t limit, i, j, cpuid_i; From 0e8916582991b9fd0b94850a8444b8b80d0a0955 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Mon, 10 Dec 2018 16:02:50 -0200 Subject: [PATCH 4/4] i386: Add "stibp" flag name The STIBP flag may be supported by the host KVM module, so QEMU can allow it to be configured manually, and it can be exposed to guests when using "-cpu host". No additional migration code is required because the whole contents of spec_ctrl is already migrated in the "cpu/spec_ctrl" section. Corresponding KVM patch was submitted at: https://lore.kernel.org/lkml/20181205191956.31480-1-ehabkost@redhat.com/ Signed-off-by: Eduardo Habkost Message-Id: <20181210180250.31299-1-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost --- target/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 86a934d450..12f559b6af 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1042,7 +1042,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { NULL, NULL, NULL, NULL, NULL, NULL, "pconfig", NULL, NULL, NULL, NULL, NULL, - NULL, NULL, "spec-ctrl", NULL, + NULL, NULL, "spec-ctrl", "stibp", NULL, "arch-capabilities", NULL, "ssbd", }, .cpuid = {