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host-utils: move udiv_qrnnd() to host-utils
Move udiv_qrnnd() from include/fpu/softfloat-macros.h to host-utils, so it can be reused by divu128(). Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211025191154.350831-3-luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Luis Pires
Richard Henderson
parent
9276a31c34
commit
8ac2d6c526
2 changed files with 81 additions and 82 deletions
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@ -8,7 +8,6 @@
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* so some portions are provided under:
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* the SoftFloat-2a license
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* the BSD license
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* GPL-v2-or-later
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*
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* Any future contributions to this file after December 1st 2014 will be
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* taken to be licensed under the Softfloat-2a license unless specifically
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@ -75,10 +74,6 @@ this code that are retained.
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* Portions of this work are licensed under the terms of the GNU GPL,
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* version 2 or later. See the COPYING file in the top-level directory.
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*/
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#ifndef FPU_SOFTFLOAT_MACROS_H
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#define FPU_SOFTFLOAT_MACROS_H
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@ -585,83 +580,6 @@ static inline uint64_t estimateDiv128To64(uint64_t a0, uint64_t a1, uint64_t b)
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}
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/* From the GNU Multi Precision Library - longlong.h __udiv_qrnnd
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* (https://gmplib.org/repo/gmp/file/tip/longlong.h)
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*
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* Licensed under the GPLv2/LGPLv3
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*/
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static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1,
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uint64_t n0, uint64_t d)
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{
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#if defined(__x86_64__)
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uint64_t q;
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asm("divq %4" : "=a"(q), "=d"(*r) : "0"(n0), "1"(n1), "rm"(d));
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return q;
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#elif defined(__s390x__) && !defined(__clang__)
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/* Need to use a TImode type to get an even register pair for DLGR. */
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unsigned __int128 n = (unsigned __int128)n1 << 64 | n0;
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asm("dlgr %0, %1" : "+r"(n) : "r"(d));
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*r = n >> 64;
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return n;
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#elif defined(_ARCH_PPC64) && defined(_ARCH_PWR7)
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/* From Power ISA 2.06, programming note for divdeu. */
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uint64_t q1, q2, Q, r1, r2, R;
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asm("divdeu %0,%2,%4; divdu %1,%3,%4"
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: "=&r"(q1), "=r"(q2)
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: "r"(n1), "r"(n0), "r"(d));
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r1 = -(q1 * d); /* low part of (n1<<64) - (q1 * d) */
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r2 = n0 - (q2 * d);
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Q = q1 + q2;
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R = r1 + r2;
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if (R >= d || R < r2) { /* overflow implies R > d */
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Q += 1;
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R -= d;
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}
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*r = R;
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return Q;
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#else
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uint64_t d0, d1, q0, q1, r1, r0, m;
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d0 = (uint32_t)d;
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d1 = d >> 32;
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r1 = n1 % d1;
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q1 = n1 / d1;
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m = q1 * d0;
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r1 = (r1 << 32) | (n0 >> 32);
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if (r1 < m) {
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q1 -= 1;
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r1 += d;
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if (r1 >= d) {
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if (r1 < m) {
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q1 -= 1;
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r1 += d;
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}
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}
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}
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r1 -= m;
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r0 = r1 % d1;
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q0 = r1 / d1;
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m = q0 * d0;
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r0 = (r0 << 32) | (uint32_t)n0;
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if (r0 < m) {
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q0 -= 1;
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r0 += d;
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if (r0 >= d) {
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if (r0 < m) {
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q0 -= 1;
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r0 += d;
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}
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}
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}
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r0 -= m;
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*r = r0;
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return (q1 << 32) | q0;
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#endif
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}
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/*----------------------------------------------------------------------------
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| Returns an approximation to the square root of the 32-bit significand given
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| by `a'. Considered as an integer, `a' must be at least 2^31. If bit 0 of
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@ -23,6 +23,10 @@
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* THE SOFTWARE.
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*/
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/* Portions of this work are licensed under the terms of the GNU GPL,
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* version 2 or later. See the COPYING file in the top-level directory.
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*/
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#ifndef HOST_UTILS_H
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#define HOST_UTILS_H
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@ -726,4 +730,81 @@ void urshift(uint64_t *plow, uint64_t *phigh, int32_t shift);
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*/
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void ulshift(uint64_t *plow, uint64_t *phigh, int32_t shift, bool *overflow);
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/* From the GNU Multi Precision Library - longlong.h __udiv_qrnnd
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* (https://gmplib.org/repo/gmp/file/tip/longlong.h)
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*
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* Licensed under the GPLv2/LGPLv3
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*/
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static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1,
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uint64_t n0, uint64_t d)
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{
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#if defined(__x86_64__)
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uint64_t q;
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asm("divq %4" : "=a"(q), "=d"(*r) : "0"(n0), "1"(n1), "rm"(d));
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return q;
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#elif defined(__s390x__) && !defined(__clang__)
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/* Need to use a TImode type to get an even register pair for DLGR. */
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unsigned __int128 n = (unsigned __int128)n1 << 64 | n0;
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asm("dlgr %0, %1" : "+r"(n) : "r"(d));
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*r = n >> 64;
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return n;
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#elif defined(_ARCH_PPC64) && defined(_ARCH_PWR7)
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/* From Power ISA 2.06, programming note for divdeu. */
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uint64_t q1, q2, Q, r1, r2, R;
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asm("divdeu %0,%2,%4; divdu %1,%3,%4"
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: "=&r"(q1), "=r"(q2)
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: "r"(n1), "r"(n0), "r"(d));
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r1 = -(q1 * d); /* low part of (n1<<64) - (q1 * d) */
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r2 = n0 - (q2 * d);
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Q = q1 + q2;
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R = r1 + r2;
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if (R >= d || R < r2) { /* overflow implies R > d */
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Q += 1;
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R -= d;
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}
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*r = R;
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return Q;
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#else
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uint64_t d0, d1, q0, q1, r1, r0, m;
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d0 = (uint32_t)d;
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d1 = d >> 32;
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r1 = n1 % d1;
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q1 = n1 / d1;
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m = q1 * d0;
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r1 = (r1 << 32) | (n0 >> 32);
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if (r1 < m) {
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q1 -= 1;
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r1 += d;
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if (r1 >= d) {
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if (r1 < m) {
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q1 -= 1;
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r1 += d;
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}
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}
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}
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r1 -= m;
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r0 = r1 % d1;
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q0 = r1 / d1;
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m = q0 * d0;
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r0 = (r0 << 32) | (uint32_t)n0;
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if (r0 < m) {
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q0 -= 1;
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r0 += d;
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if (r0 >= d) {
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if (r0 < m) {
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q0 -= 1;
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r0 += d;
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}
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}
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}
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r0 -= m;
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*r = r0;
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return (q1 << 32) | q0;
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#endif
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}
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#endif
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