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tcg/tci: Fix big-endian return register ordering
We expect the backend to require register pairs in host-endian ordering, thus for big-endian the first register of a pair contains the high part. We were forcing R0 to contain the low part for calls. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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tcg/tci.c
21
tcg/tci.c
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@ -520,27 +520,28 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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ffi_call(pptr[1], pptr[0], stack, call_slots);
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}
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/* Any result winds up "left-aligned" in the stack[0] slot. */
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switch (len) {
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case 0: /* void */
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break;
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case 1: /* uint32_t */
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/*
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* The result winds up "left-aligned" in the stack[0] slot.
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* Note that libffi has an odd special case in that it will
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* always widen an integral result to ffi_arg.
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*/
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if (sizeof(ffi_arg) == 4) {
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regs[TCG_REG_R0] = *(uint32_t *)stack;
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break;
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}
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/* fall through */
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case 2: /* uint64_t */
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if (TCG_TARGET_REG_BITS == 32) {
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tci_write_reg64(regs, TCG_REG_R1, TCG_REG_R0, stack[0]);
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if (sizeof(ffi_arg) == 8) {
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regs[TCG_REG_R0] = (uint32_t)stack[0];
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} else {
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regs[TCG_REG_R0] = stack[0];
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regs[TCG_REG_R0] = *(uint32_t *)stack;
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}
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break;
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case 2: /* uint64_t */
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/*
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* For TCG_TARGET_REG_BITS == 32, the register pair
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* must stay in host memory order.
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*/
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memcpy(®s[TCG_REG_R0], stack, 8);
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break;
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default:
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g_assert_not_reached();
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}
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