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ahci: Add test_pci_spec to ahci-test.
Adds a specification adherence test for AHCI where the boot-up values for the PCI configuration space are compared against the AHCI 1.3 specification. This test does not itself attempt to engage the device. Signed-off-by: John Snow <jsnow@redhat.com> Message-id: 1408643079-30675-4-git-send-email-jsnow@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
John Snow
Stefan Hajnoczi
parent
c8b5b20f81
commit
8840a843dc
1 changed files with 299 additions and 6 deletions
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@ -25,7 +25,7 @@
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#include <stdint.h>
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#include <string.h>
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#include <stdio.h>
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#include <getopt.h>
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#include <glib.h>
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#include "libqtest.h"
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@ -43,15 +43,36 @@
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/*** Supplementary PCI Config Space IDs & Masks ***/
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#define PCI_DEVICE_ID_INTEL_Q35_AHCI (0x2922)
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#define PCI_MSI_FLAGS_RESERVED (0xFF00)
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#define PCI_PM_CTRL_RESERVED (0xFC)
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#define PCI_BCC(REG32) ((REG32) >> 24)
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#define PCI_PI(REG32) (((REG32) >> 8) & 0xFF)
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#define PCI_SCC(REG32) (((REG32) >> 16) & 0xFF)
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/*** Recognized AHCI Device Types ***/
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#define AHCI_INTEL_ICH9 (PCI_DEVICE_ID_INTEL_Q35_AHCI << 16 | \
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PCI_VENDOR_ID_INTEL)
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/*** Globals ***/
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static QGuestAllocator *guest_malloc;
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static QPCIBus *pcibus;
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static char tmp_path[] = "/tmp/qtest.XXXXXX";
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static bool ahci_pedantic;
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static uint32_t ahci_fingerprint;
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/*** Macro Utilities ***/
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#define ASSERT_BIT_SET(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
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#define ASSERT_BIT_CLEAR(data, mask) g_assert_cmphex((data) & (mask), ==, 0)
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/*** Function Declarations ***/
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static QPCIDevice *get_ahci_device(void);
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static void free_ahci_device(QPCIDevice *dev);
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static void ahci_test_pci_spec(QPCIDevice *ahci);
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static void ahci_test_pci_caps(QPCIDevice *ahci, uint16_t header,
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uint8_t offset);
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static void ahci_test_satacap(QPCIDevice *ahci, uint8_t offset);
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static void ahci_test_msicap(QPCIDevice *ahci, uint8_t offset);
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static void ahci_test_pmcap(QPCIDevice *ahci, uint8_t offset);
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/*** Utilities ***/
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@ -61,7 +82,6 @@ static void free_ahci_device(QPCIDevice *dev);
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static QPCIDevice *get_ahci_device(void)
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{
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QPCIDevice *ahci;
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uint16_t vendor_id, device_id;
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pcibus = qpci_init_pc();
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@ -69,11 +89,15 @@ static QPCIDevice *get_ahci_device(void)
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ahci = qpci_device_find(pcibus, QPCI_DEVFN(0x1F, 0x02));
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g_assert(ahci != NULL);
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vendor_id = qpci_config_readw(ahci, PCI_VENDOR_ID);
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device_id = qpci_config_readw(ahci, PCI_DEVICE_ID);
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ahci_fingerprint = qpci_config_readl(ahci, PCI_VENDOR_ID);
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g_assert_cmphex(vendor_id, ==, PCI_VENDOR_ID_INTEL);
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g_assert_cmphex(device_id, ==, PCI_DEVICE_ID_INTEL_Q35_AHCI);
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switch (ahci_fingerprint) {
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case AHCI_INTEL_ICH9:
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break;
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default:
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/* Unknown device. */
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g_assert_not_reached();
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}
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return ahci;
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}
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@ -145,6 +169,239 @@ static void ahci_shutdown(QPCIDevice *ahci)
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qtest_shutdown();
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}
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/*** Specification Adherence Tests ***/
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/**
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* Implementation for test_pci_spec. Ensures PCI configuration space is sane.
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*/
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static void ahci_test_pci_spec(QPCIDevice *ahci)
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{
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uint8_t datab;
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uint16_t data;
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uint32_t datal;
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/* Most of these bits should start cleared until we turn them on. */
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data = qpci_config_readw(ahci, PCI_COMMAND);
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ASSERT_BIT_CLEAR(data, PCI_COMMAND_MEMORY);
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ASSERT_BIT_CLEAR(data, PCI_COMMAND_MASTER);
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ASSERT_BIT_CLEAR(data, PCI_COMMAND_SPECIAL); /* Reserved */
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ASSERT_BIT_CLEAR(data, PCI_COMMAND_VGA_PALETTE); /* Reserved */
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ASSERT_BIT_CLEAR(data, PCI_COMMAND_PARITY);
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ASSERT_BIT_CLEAR(data, PCI_COMMAND_WAIT); /* Reserved */
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ASSERT_BIT_CLEAR(data, PCI_COMMAND_SERR);
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ASSERT_BIT_CLEAR(data, PCI_COMMAND_FAST_BACK);
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ASSERT_BIT_CLEAR(data, PCI_COMMAND_INTX_DISABLE);
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ASSERT_BIT_CLEAR(data, 0xF800); /* Reserved */
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data = qpci_config_readw(ahci, PCI_STATUS);
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ASSERT_BIT_CLEAR(data, 0x01 | 0x02 | 0x04); /* Reserved */
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ASSERT_BIT_CLEAR(data, PCI_STATUS_INTERRUPT);
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ASSERT_BIT_SET(data, PCI_STATUS_CAP_LIST); /* must be set */
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ASSERT_BIT_CLEAR(data, PCI_STATUS_UDF); /* Reserved */
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ASSERT_BIT_CLEAR(data, PCI_STATUS_PARITY);
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ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_TARGET_ABORT);
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ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_TARGET_ABORT);
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ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_MASTER_ABORT);
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ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_SYSTEM_ERROR);
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ASSERT_BIT_CLEAR(data, PCI_STATUS_DETECTED_PARITY);
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/* RID occupies the low byte, CCs occupy the high three. */
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datal = qpci_config_readl(ahci, PCI_CLASS_REVISION);
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if (ahci_pedantic) {
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/* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00,
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* Though in practice this is likely seldom true. */
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ASSERT_BIT_CLEAR(datal, 0xFF);
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}
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/* BCC *must* equal 0x01. */
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g_assert_cmphex(PCI_BCC(datal), ==, 0x01);
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if (PCI_SCC(datal) == 0x01) {
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/* IDE */
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ASSERT_BIT_SET(0x80000000, datal);
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ASSERT_BIT_CLEAR(0x60000000, datal);
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} else if (PCI_SCC(datal) == 0x04) {
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/* RAID */
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g_assert_cmphex(PCI_PI(datal), ==, 0);
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} else if (PCI_SCC(datal) == 0x06) {
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/* AHCI */
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g_assert_cmphex(PCI_PI(datal), ==, 0x01);
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} else {
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g_assert_not_reached();
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}
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datab = qpci_config_readb(ahci, PCI_CACHE_LINE_SIZE);
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g_assert_cmphex(datab, ==, 0);
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datab = qpci_config_readb(ahci, PCI_LATENCY_TIMER);
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g_assert_cmphex(datab, ==, 0);
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/* Only the bottom 7 bits must be off. */
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datab = qpci_config_readb(ahci, PCI_HEADER_TYPE);
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ASSERT_BIT_CLEAR(datab, 0x7F);
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/* BIST is optional, but the low 7 bits must always start off regardless. */
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datab = qpci_config_readb(ahci, PCI_BIST);
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ASSERT_BIT_CLEAR(datab, 0x7F);
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/* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */
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datal = qpci_config_readl(ahci, PCI_BASE_ADDRESS_5);
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g_assert_cmphex(datal, ==, 0);
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qpci_config_writel(ahci, PCI_BASE_ADDRESS_5, 0xFFFFFFFF);
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datal = qpci_config_readl(ahci, PCI_BASE_ADDRESS_5);
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/* ABAR must be 32-bit, memory mapped, non-prefetchable and
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* must be >= 512 bytes. To that end, bits 0-8 must be off. */
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ASSERT_BIT_CLEAR(datal, 0xFF);
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/* Capability list MUST be present, */
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datal = qpci_config_readl(ahci, PCI_CAPABILITY_LIST);
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/* But these bits are reserved. */
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ASSERT_BIT_CLEAR(datal, ~0xFF);
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g_assert_cmphex(datal, !=, 0);
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/* Check specification adherence for capability extenstions. */
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data = qpci_config_readw(ahci, datal);
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switch (ahci_fingerprint) {
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case AHCI_INTEL_ICH9:
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/* Intel ICH9 Family Datasheet 14.1.19 p.550 */
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g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_MSI);
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break;
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default:
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/* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */
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g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_PM);
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}
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ahci_test_pci_caps(ahci, data, (uint8_t)datal);
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/* Reserved. */
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datal = qpci_config_readl(ahci, PCI_CAPABILITY_LIST + 4);
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g_assert_cmphex(datal, ==, 0);
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/* IPIN might vary, but ILINE must be off. */
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datab = qpci_config_readb(ahci, PCI_INTERRUPT_LINE);
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g_assert_cmphex(datab, ==, 0);
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}
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/**
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* Test PCI capabilities for AHCI specification adherence.
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*/
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static void ahci_test_pci_caps(QPCIDevice *ahci, uint16_t header,
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uint8_t offset)
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{
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uint8_t cid = header & 0xFF;
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uint8_t next = header >> 8;
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g_test_message("CID: %02x; next: %02x", cid, next);
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switch (cid) {
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case PCI_CAP_ID_PM:
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ahci_test_pmcap(ahci, offset);
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break;
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case PCI_CAP_ID_MSI:
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ahci_test_msicap(ahci, offset);
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break;
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case PCI_CAP_ID_SATA:
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ahci_test_satacap(ahci, offset);
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break;
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default:
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g_test_message("Unknown CAP 0x%02x", cid);
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}
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if (next) {
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ahci_test_pci_caps(ahci, qpci_config_readw(ahci, next), next);
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}
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}
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/**
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* Test SATA PCI capabilitity for AHCI specification adherence.
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*/
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static void ahci_test_satacap(QPCIDevice *ahci, uint8_t offset)
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{
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uint16_t dataw;
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uint32_t datal;
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g_test_message("Verifying SATACAP");
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/* Assert that the SATACAP version is 1.0, And reserved bits are empty. */
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dataw = qpci_config_readw(ahci, offset + 2);
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g_assert_cmphex(dataw, ==, 0x10);
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/* Grab the SATACR1 register. */
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datal = qpci_config_readw(ahci, offset + 4);
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switch (datal & 0x0F) {
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case 0x04: /* BAR0 */
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case 0x05: /* BAR1 */
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case 0x06:
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case 0x07:
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case 0x08:
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case 0x09: /* BAR5 */
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case 0x0F: /* Immediately following SATACR1 in PCI config space. */
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break;
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default:
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/* Invalid BARLOC for the Index Data Pair. */
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g_assert_not_reached();
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}
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/* Reserved. */
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g_assert_cmphex((datal >> 24), ==, 0x00);
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}
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/**
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* Test MSI PCI capability for AHCI specification adherence.
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*/
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static void ahci_test_msicap(QPCIDevice *ahci, uint8_t offset)
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{
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uint16_t dataw;
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uint32_t datal;
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g_test_message("Verifying MSICAP");
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dataw = qpci_config_readw(ahci, offset + PCI_MSI_FLAGS);
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ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_ENABLE);
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ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_QSIZE);
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ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_RESERVED);
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datal = qpci_config_readl(ahci, offset + PCI_MSI_ADDRESS_LO);
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g_assert_cmphex(datal, ==, 0);
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if (dataw & PCI_MSI_FLAGS_64BIT) {
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g_test_message("MSICAP is 64bit");
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datal = qpci_config_readl(ahci, offset + PCI_MSI_ADDRESS_HI);
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g_assert_cmphex(datal, ==, 0);
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dataw = qpci_config_readw(ahci, offset + PCI_MSI_DATA_64);
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g_assert_cmphex(dataw, ==, 0);
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} else {
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g_test_message("MSICAP is 32bit");
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dataw = qpci_config_readw(ahci, offset + PCI_MSI_DATA_32);
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g_assert_cmphex(dataw, ==, 0);
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}
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}
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/**
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* Test Power Management PCI capability for AHCI specification adherence.
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*/
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static void ahci_test_pmcap(QPCIDevice *ahci, uint8_t offset)
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{
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uint16_t dataw;
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g_test_message("Verifying PMCAP");
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dataw = qpci_config_readw(ahci, offset + PCI_PM_PMC);
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ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_PME_CLOCK);
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ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_RESERVED);
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ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D1);
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ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D2);
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dataw = qpci_config_readw(ahci, offset + PCI_PM_CTRL);
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ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_STATE_MASK);
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ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_RESERVED);
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ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SEL_MASK);
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ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SCALE_MASK);
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}
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/******************************************************************************/
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/* Test Interfaces */
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/******************************************************************************/
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@ -159,6 +416,18 @@ static void test_sanity(void)
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ahci_shutdown(ahci);
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}
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/**
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* Ensure that the PCI configuration space for the AHCI device is in-line with
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* the AHCI 1.3 specification for initial values.
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*/
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static void test_pci_spec(void)
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{
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QPCIDevice *ahci;
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ahci = ahci_boot();
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ahci_test_pci_spec(ahci);
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ahci_shutdown(ahci);
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}
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/******************************************************************************/
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int main(int argc, char **argv)
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@ -166,10 +435,33 @@ int main(int argc, char **argv)
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const char *arch;
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int fd;
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int ret;
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int c;
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static struct option long_options[] = {
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{"pedantic", no_argument, 0, 'p' },
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{0, 0, 0, 0},
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};
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/* Should be first to utilize g_test functionality, So we can see errors. */
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g_test_init(&argc, &argv, NULL);
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while (1) {
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c = getopt_long(argc, argv, "", long_options, NULL);
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if (c == -1) {
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break;
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}
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switch (c) {
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case -1:
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break;
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case 'p':
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ahci_pedantic = 1;
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break;
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default:
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fprintf(stderr, "Unrecognized ahci_test option.\n");
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g_assert_not_reached();
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}
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}
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/* Check architecture */
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arch = qtest_get_arch();
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if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
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@ -186,6 +478,7 @@ int main(int argc, char **argv)
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/* Run the tests */
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qtest_add_func("/ahci/sanity", test_sanity);
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qtest_add_func("/ahci/pci_spec", test_pci_spec);
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ret = g_test_run();
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