system/qemu
system/qemu
1
0
Fork 0
mirror of https://gitlab.com/qemu-project/qemu synced 2024-11-05 20:35:44 +00:00
Code Issues Projects Releases Packages Wiki Activity

hw/misc: Add the STM32F4xx Sysconfig device

Browse source 
Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 49b01423a09cef2ca832ff73a84a996568f1a8fc.1576658572.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alistair Francis 2020-01-17 14:09:29 +00:00 committed by Peter Maydell
parent cbf01142b2
commit 870c034da0
7 changed files with 252 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
default-configs/arm-softmmu.mak
View file

@ -30,6 +30,7 @@ CONFIG_Z2=y
CONFIG_COLLIE=y
CONFIG_ASPEED_SOC=y
CONFIG_NETDUINO2=y
CONFIG_NETDUINOPLUS2=y
CONFIG_MPS2=y
CONFIG_RASPI=y
CONFIG_DIGIC=y

9
hw/arm/Kconfig
View file

@ -101,6 +101,10 @@ config NETDUINO2
bool
select STM32F205_SOC
config NETDUINOPLUS2
bool
select STM32F405_SOC
config NSERIES
bool
select OMAP
@ -307,6 +311,11 @@ config STM32F205_SOC
select STM32F2XX_ADC
select STM32F2XX_SPI
config STM32F405_SOC
bool
select ARM_V7M
select STM32F4XX_SYSCFG
config XLNX_ZYNQMP_ARM
bool
select AHCI

3
hw/misc/Kconfig
View file

@ -82,6 +82,9 @@ config IMX
config STM32F2XX_SYSCFG
bool
config STM32F4XX_SYSCFG
bool
config MIPS_ITU
bool

1
hw/misc/Makefile.objs
View file

@ -58,6 +58,7 @@ common-obj-$(CONFIG_SLAVIO) += slavio_misc.o
common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o
common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o
common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
common-obj-$(CONFIG_STM32F4XX_SYSCFG) += stm32f4xx_syscfg.o
obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o
obj-$(CONFIG_MIPS_CPS) += mips_cpc.o
obj-$(CONFIG_MIPS_ITU) += mips_itu.o

171
hw/misc/stm32f4xx_syscfg.c Normal file
View file

@ -0,0 +1,171 @@
/*
* STM32F4xx SYSCFG
*
* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "trace.h"
#include "hw/irq.h"
#include "migration/vmstate.h"
#include "hw/misc/stm32f4xx_syscfg.h"
static void stm32f4xx_syscfg_reset(DeviceState *dev)
{
STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(dev);
s->syscfg_memrmp = 0x00000000;
s->syscfg_pmc = 0x00000000;
s->syscfg_exticr[0] = 0x00000000;
s->syscfg_exticr[1] = 0x00000000;
s->syscfg_exticr[2] = 0x00000000;
s->syscfg_exticr[3] = 0x00000000;
s->syscfg_cmpcr = 0x00000000;
}
static void stm32f4xx_syscfg_set_irq(void *opaque, int irq, int level)
{
STM32F4xxSyscfgState *s = opaque;
int icrreg = irq / 4;
int startbit = (irq & 3) * 4;
uint8_t config = config = irq / 16;
trace_stm32f4xx_syscfg_set_irq(irq / 16, irq % 16, level);
g_assert(icrreg < SYSCFG_NUM_EXTICR);
if (extract32(s->syscfg_exticr[icrreg], startbit, 4) == config) {
qemu_set_irq(s->gpio_out[irq], level);
trace_stm32f4xx_pulse_exti(irq);
}
}
static uint64_t stm32f4xx_syscfg_read(void *opaque, hwaddr addr,
unsigned int size)
{
STM32F4xxSyscfgState *s = opaque;
trace_stm32f4xx_syscfg_read(addr);
switch (addr) {
case SYSCFG_MEMRMP:
return s->syscfg_memrmp;
case SYSCFG_PMC:
return s->syscfg_pmc;
case SYSCFG_EXTICR1...SYSCFG_EXTICR4:
return s->syscfg_exticr[addr / 4 - SYSCFG_EXTICR1 / 4];
case SYSCFG_CMPCR:
return s->syscfg_cmpcr;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
return 0;
}
}
static void stm32f4xx_syscfg_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
STM32F4xxSyscfgState *s = opaque;
uint32_t value = val64;
trace_stm32f4xx_syscfg_write(value, addr);
switch (addr) {
case SYSCFG_MEMRMP:
qemu_log_mask(LOG_UNIMP,
"%s: Changing the memory mapping isn't supported " \
"in QEMU\n", __func__);
return;
case SYSCFG_PMC:
qemu_log_mask(LOG_UNIMP,
"%s: Changing the memory mapping isn't supported " \
"in QEMU\n", __func__);
return;
case SYSCFG_EXTICR1...SYSCFG_EXTICR4:
s->syscfg_exticr[addr / 4 - SYSCFG_EXTICR1 / 4] = (value & 0xFFFF);
return;
case SYSCFG_CMPCR:
s->syscfg_cmpcr = value;
return;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
}
}
static const MemoryRegionOps stm32f4xx_syscfg_ops = {
.read = stm32f4xx_syscfg_read,
.write = stm32f4xx_syscfg_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void stm32f4xx_syscfg_init(Object *obj)
{
STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(obj);
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
memory_region_init_io(&s->mmio, obj, &stm32f4xx_syscfg_ops, s,
TYPE_STM32F4XX_SYSCFG, 0x400);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
qdev_init_gpio_in(DEVICE(obj), stm32f4xx_syscfg_set_irq, 16 * 9);
qdev_init_gpio_out(DEVICE(obj), s->gpio_out, 16);
}
static const VMStateDescription vmstate_stm32f4xx_syscfg = {
.name = TYPE_STM32F4XX_SYSCFG,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(syscfg_memrmp, STM32F4xxSyscfgState),
VMSTATE_UINT32(syscfg_pmc, STM32F4xxSyscfgState),
VMSTATE_UINT32_ARRAY(syscfg_exticr, STM32F4xxSyscfgState,
SYSCFG_NUM_EXTICR),
VMSTATE_UINT32(syscfg_cmpcr, STM32F4xxSyscfgState),
VMSTATE_END_OF_LIST()
}
};
static void stm32f4xx_syscfg_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = stm32f4xx_syscfg_reset;
dc->vmsd = &vmstate_stm32f4xx_syscfg;
}
static const TypeInfo stm32f4xx_syscfg_info = {
.name = TYPE_STM32F4XX_SYSCFG,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(STM32F4xxSyscfgState),
.instance_init = stm32f4xx_syscfg_init,
.class_init = stm32f4xx_syscfg_class_init,
};
static void stm32f4xx_syscfg_register_types(void)
{
type_register_static(&stm32f4xx_syscfg_info);
}
type_init(stm32f4xx_syscfg_register_types)

6
hw/misc/trace-events
View file

@ -84,6 +84,12 @@ mos6522_set_sr_int(void) "set sr_int"
mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64
mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x"
# stm32f4xx_syscfg
stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
# tz-mpc.c
tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u"
tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u"

61
include/hw/misc/stm32f4xx_syscfg.h Normal file
View file

@ -0,0 +1,61 @@
/*
* STM32F4xx SYSCFG
*
* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HW_STM_SYSCFG_H
#define HW_STM_SYSCFG_H
#include "hw/sysbus.h"
#include "hw/hw.h"
#define SYSCFG_MEMRMP 0x00
#define SYSCFG_PMC 0x04
#define SYSCFG_EXTICR1 0x08
#define SYSCFG_EXTICR2 0x0C
#define SYSCFG_EXTICR3 0x10
#define SYSCFG_EXTICR4 0x14
#define SYSCFG_CMPCR 0x20
#define TYPE_STM32F4XX_SYSCFG "stm32f4xx-syscfg"
#define STM32F4XX_SYSCFG(obj) \
OBJECT_CHECK(STM32F4xxSyscfgState, (obj), TYPE_STM32F4XX_SYSCFG)
#define SYSCFG_NUM_EXTICR 4
typedef struct {
/* <private> */
SysBusDevice parent_obj;
/* <public> */
MemoryRegion mmio;
uint32_t syscfg_memrmp;
uint32_t syscfg_pmc;
uint32_t syscfg_exticr[SYSCFG_NUM_EXTICR];
uint32_t syscfg_cmpcr;
qemu_irq irq;
qemu_irq gpio_out[16];
} STM32F4xxSyscfgState;
#endif