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target-arm queue:

Browse source 
* enable FEAT_RNG on Neoverse-N2
  * hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ
  * Fix SME FMOPA (16-bit), BFMOPA
  * hw/core/machine: Constify MachineClass::valid_cpu_types[]
  * stm32f* machines: Report error when user asks for wrong CPU type
  * hw/arm/fsl-imx: Do not ignore Error argument
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 =thIa
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Merge tag 'pull-target-arm-20231121' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * enable FEAT_RNG on Neoverse-N2
 * hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ
 * Fix SME FMOPA (16-bit), BFMOPA
 * hw/core/machine: Constify MachineClass::valid_cpu_types[]
 * stm32f* machines: Report error when user asks for wrong CPU type
 * hw/arm/fsl-imx: Do not ignore Error argument

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# =thIa
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 21 Nov 2023 05:21:42 EST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20231121' of https://git.linaro.org/people/pmaydell/qemu-arm:
  hw/arm/fsl-imx: Do not ignore Error argument
  hw/arm/stm32f100: Report error when incorrect CPU is used
  hw/arm/stm32f205: Report error when incorrect CPU is used
  hw/arm/stm32f405: Report error when incorrect CPU is used
  hw/core/machine: Constify MachineClass::valid_cpu_types[]
  target/arm: Fix SME FMOPA (16-bit), BFMOPA
  hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ
  target/arm: enable FEAT_RNG on Neoverse-N2

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2023-11-21 06:24:53 -05:00
parent 19c63383a7 0cbb56c236
commit 85f1051248
18 changed files with 56 additions and 68 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
hw/arm/fsl-imx25.c
View file

@ -169,7 +169,8 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
epit_table[i].irq));
}
object_property_set_uint(OBJECT(&s->fec), "phy-num", s->phy_num, &err);
object_property_set_uint(OBJECT(&s->fec), "phy-num", s->phy_num,
&error_abort);
qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->fec), errp)) {

3
hw/arm/fsl-imx6.c
View file

@ -379,7 +379,8 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
spi_table[i].irq));
}
object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, &err);
object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num,
&error_abort);
qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->eth), errp)) {
return;

7
hw/arm/netduino2.c
View file

@ -44,7 +44,6 @@ static void netduino2_init(MachineState *machine)
clock_set_hz(sysclk, SYSCLK_FRQ);
dev = qdev_new(TYPE_STM32F205_SOC);
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@ -54,8 +53,14 @@ static void netduino2_init(MachineState *machine)
static void netduino2_machine_init(MachineClass *mc)
{
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m3"),
NULL
};
mc->desc = "Netduino 2 Machine (Cortex-M3)";
mc->init = netduino2_init;
mc->valid_cpu_types = valid_cpu_types;
mc->ignore_memory_transaction_failures = true;
}

7
hw/arm/netduinoplus2.c
View file

@ -44,7 +44,6 @@ static void netduinoplus2_init(MachineState *machine)
clock_set_hz(sysclk, SYSCLK_FRQ);
dev = qdev_new(TYPE_STM32F405_SOC);
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@ -55,8 +54,14 @@ static void netduinoplus2_init(MachineState *machine)
static void netduinoplus2_machine_init(MachineClass *mc)
{
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m4"),
NULL
};
mc->desc = "Netduino Plus 2 Machine (Cortex-M4)";
mc->init = netduinoplus2_init;
mc->valid_cpu_types = valid_cpu_types;
}
DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init)

8
hw/arm/olimex-stm32-h405.c
View file

@ -47,7 +47,6 @@ static void olimex_stm32_h405_init(MachineState *machine)
clock_set_hz(sysclk, SYSCLK_FRQ);
dev = qdev_new(TYPE_STM32F405_SOC);
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@ -58,9 +57,14 @@ static void olimex_stm32_h405_init(MachineState *machine)
static void olimex_stm32_h405_machine_init(MachineClass *mc)
{
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m4"),
NULL
};
mc->desc = "Olimex STM32-H405 (Cortex-M4)";
mc->init = olimex_stm32_h405_init;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
mc->valid_cpu_types = valid_cpu_types;
/* SRAM pre-allocated as part of the SoC instantiation */
mc->default_ram_size = 0;

9
hw/arm/stm32f100_soc.c
View file

@ -115,7 +115,7 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
/* Init ARMv7m */
armv7m = DEVICE(&s->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 61);
qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
qdev_prop_set_bit(armv7m, "enable-bitband", true);
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
qdev_connect_clock_in(armv7m, "refclk", s->refclk);
@ -180,17 +180,12 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
create_unimplemented_device("CRC", 0x40023000, 0x400);
}
static Property stm32f100_soc_properties[] = {
DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type),
DEFINE_PROP_END_OF_LIST(),
};
static void stm32f100_soc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = stm32f100_soc_realize;
device_class_set_props(dc, stm32f100_soc_properties);
/* No vmstate or reset required: device has no internal state */
}
static const TypeInfo stm32f100_soc_info = {

9
hw/arm/stm32f205_soc.c
View file

@ -127,7 +127,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
armv7m = DEVICE(&s->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 96);
qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
qdev_prop_set_bit(armv7m, "enable-bitband", true);
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
qdev_connect_clock_in(armv7m, "refclk", s->refclk);
@ -201,17 +201,12 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
}
}
static Property stm32f205_soc_properties[] = {
DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type),
DEFINE_PROP_END_OF_LIST(),
};
static void stm32f205_soc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = stm32f205_soc_realize;
device_class_set_props(dc, stm32f205_soc_properties);
/* No vmstate or reset required: device has no internal state */
}
static const TypeInfo stm32f205_soc_info = {

8
hw/arm/stm32f405_soc.c
View file

@ -149,7 +149,7 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
armv7m = DEVICE(&s->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 96);
qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
qdev_prop_set_bit(armv7m, "enable-bitband", true);
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
qdev_connect_clock_in(armv7m, "refclk", s->refclk);
@ -287,17 +287,11 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
create_unimplemented_device("RNG", 0x50060800, 0x400);
}
static Property stm32f405_soc_properties[] = {
DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type),
DEFINE_PROP_END_OF_LIST(),
};
static void stm32f405_soc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = stm32f405_soc_realize;
device_class_set_props(dc, stm32f405_soc_properties);
/* No vmstate or reset required: device has no internal state */
}

7
hw/arm/stm32vldiscovery.c
View file

@ -47,7 +47,6 @@ static void stm32vldiscovery_init(MachineState *machine)
clock_set_hz(sysclk, SYSCLK_FRQ);
dev = qdev_new(TYPE_STM32F100_SOC);
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@ -58,8 +57,14 @@ static void stm32vldiscovery_init(MachineState *machine)
static void stm32vldiscovery_machine_init(MachineClass *mc)
{
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m3"),
NULL
};
mc->desc = "ST STM32VLDISCOVERY (Cortex-M3)";
mc->init = stm32vldiscovery_init;
mc->valid_cpu_types = valid_cpu_types;
}
DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init)

22
hw/hppa/machine.c
View file

@ -672,19 +672,18 @@ static void hppa_nmi(NMIState *n, int cpu_index, Error **errp)
}
}
static const char *HP_B160L_machine_valid_cpu_types[] = {
TYPE_HPPA_CPU,
NULL
};
static void HP_B160L_machine_init_class_init(ObjectClass *oc, void *data)
{
static const char * const valid_cpu_types[] = {
TYPE_HPPA_CPU,
NULL
};
MachineClass *mc = MACHINE_CLASS(oc);
NMIClass *nc = NMI_CLASS(oc);
mc->desc = "HP B160L workstation";
mc->default_cpu_type = TYPE_HPPA_CPU;
mc->valid_cpu_types = HP_B160L_machine_valid_cpu_types;
mc->valid_cpu_types = valid_cpu_types;
mc->init = machine_HP_B160L_init;
mc->reset = hppa_machine_reset;
mc->block_default_type = IF_SCSI;
@ -709,19 +708,18 @@ static const TypeInfo HP_B160L_machine_init_typeinfo = {
},
};
static const char *HP_C3700_machine_valid_cpu_types[] = {
TYPE_HPPA64_CPU,
NULL
};
static void HP_C3700_machine_init_class_init(ObjectClass *oc, void *data)
{
static const char * const valid_cpu_types[] = {
TYPE_HPPA64_CPU,
NULL
};
MachineClass *mc = MACHINE_CLASS(oc);
NMIClass *nc = NMI_CLASS(oc);
mc->desc = "HP C3700 workstation";
mc->default_cpu_type = TYPE_HPPA64_CPU;
mc->valid_cpu_types = HP_C3700_machine_valid_cpu_types;
mc->valid_cpu_types = valid_cpu_types;
mc->init = machine_HP_C3700_init;
mc->reset = hppa_machine_reset;
mc->block_default_type = IF_SCSI;

4
hw/intc/arm_gicv3_cpuif.c
View file

@ -146,7 +146,7 @@ static uint32_t icv_fullprio_mask(GICv3CPUState *cs)
* with the group priority, whose mask depends on the value of VBPR
* for the interrupt group.)
*/
return ~0U << (8 - cs->vpribits);
return (~0U << (8 - cs->vpribits)) & 0xff;
}
static int ich_highest_active_virt_prio(GICv3CPUState *cs)
@ -803,7 +803,7 @@ static uint32_t icc_fullprio_mask(GICv3CPUState *cs)
* with the group priority, whose mask depends on the value of BPR
* for the interrupt group.)
*/
return ~0U << (8 - cs->pribits);
return (~0U << (8 - cs->pribits)) & 0xff;
}
static inline int icc_min_bpr(GICv3CPUState *cs)

11
hw/m68k/q800.c
View file

@ -726,19 +726,18 @@ static GlobalProperty hw_compat_q800[] = {
};
static const size_t hw_compat_q800_len = G_N_ELEMENTS(hw_compat_q800);
static const char *q800_machine_valid_cpu_types[] = {
M68K_CPU_TYPE_NAME("m68040"),
NULL
};
static void q800_machine_class_init(ObjectClass *oc, void *data)
{
static const char * const valid_cpu_types[] = {
M68K_CPU_TYPE_NAME("m68040"),
NULL
};
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Macintosh Quadra 800";
mc->init = q800_machine_init;
mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040");
mc->valid_cpu_types = q800_machine_valid_cpu_types;
mc->valid_cpu_types = valid_cpu_types;
mc->max_cpus = 1;
mc->block_default_type = IF_SCSI;
mc->default_ram_id = "m68k_mac.ram";

4
include/hw/arm/stm32f100_soc.h
View file

@ -43,12 +43,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC)
#define SRAM_SIZE (8 * 1024)
struct STM32F100State {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
char *cpu_type;
ARMv7MState armv7m;
STM32F2XXUsartState usart[STM_NUM_USARTS];

4
include/hw/arm/stm32f205_soc.h
View file

@ -49,11 +49,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F205State, STM32F205_SOC)
#define SRAM_SIZE (128 * 1024)
struct STM32F205State {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
char *cpu_type;
ARMv7MState armv7m;

4
include/hw/arm/stm32f405_soc.h
View file

@ -51,11 +51,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC)
#define CCM_SIZE (64 * 1024)
struct STM32F405State {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
char *cpu_type;
ARMv7MState armv7m;

2
include/hw/boards.h
View file

@ -273,7 +273,7 @@ struct MachineClass {
bool has_hotpluggable_cpus;
bool ignore_memory_transaction_failures;
int numa_mem_align_shift;
const char **valid_cpu_types;
const char * const *valid_cpu_types;
strList *allowed_dynamic_sysbus_devices;
bool auto_enable_numa_with_memhp;
bool auto_enable_numa_with_memdev;

2
target/arm/tcg/cpu64.c
View file

@ -1018,7 +1018,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
cpu->isar.id_aa64dfr1 = 0;
cpu->id_aa64afr0 = 0;
cpu->id_aa64afr1 = 0;
cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */
cpu->isar.id_aa64isar0 = 0x1221111110212120ull; /* with Crypto and FEAT_RNG */
cpu->isar.id_aa64isar1 = 0x0011111101211052ull;
cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;

10
target/arm/tcg/sme_helper.c
View file

@ -1037,10 +1037,9 @@ void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn,
m = f16mop_adj_pair(m, pcol, 0);
*a = f16_dotadd(*a, n, m, &fpst_std, &fpst_odd);
col += 4;
pcol >>= 4;
}
col += 4;
pcol >>= 4;
} while (col & 15);
}
row += 4;
@ -1073,10 +1072,9 @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn,
m = f16mop_adj_pair(m, pcol, 0);
*a = bfdotadd(*a, n, m);
col += 4;
pcol >>= 4;
}
col += 4;
pcol >>= 4;
} while (col & 15);
}
row += 4;