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net: cadence_gem: Add macro with max number of descriptor words
Add macro with max number of DMA descriptor words. No functional change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20181011021931.4249-5-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -1042,7 +1042,7 @@ static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet,
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*/
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static void gem_transmit(CadenceGEMState *s)
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{
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uint32_t desc[2];
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uint32_t desc[DESC_MAX_NUM_WORDS];
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hwaddr packet_desc_addr;
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uint8_t tx_packet[2048];
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uint8_t *p;
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@ -1108,7 +1108,7 @@ static void gem_transmit(CadenceGEMState *s)
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/* Last descriptor for this packet; hand the whole thing off */
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if (tx_desc_get_last(desc)) {
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uint32_t desc_first[2];
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uint32_t desc_first[DESC_MAX_NUM_WORDS];
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/* Modify the 1st descriptor of this packet to be owned by
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* the processor.
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@ -32,6 +32,9 @@
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#define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM address */
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/* Max number of words in a DMA descriptor. */
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#define DESC_MAX_NUM_WORDS 2
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#define MAX_PRIORITY_QUEUES 8
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#define MAX_TYPE1_SCREENERS 16
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#define MAX_TYPE2_SCREENERS 16
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@ -74,7 +77,7 @@ typedef struct CadenceGEMState {
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uint8_t can_rx_state; /* Debug only */
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uint32_t rx_desc[MAX_PRIORITY_QUEUES][2];
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uint32_t rx_desc[MAX_PRIORITY_QUEUES][DESC_MAX_NUM_WORDS];
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bool sar_active[4];
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} CadenceGEMState;
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