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Hexagon (target/hexagon) compile all debug code
Change #if HEX_DEBUG to if (HEX_DEBUG) so the debug code doesn't bit rot Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-17-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
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85580a6557
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@ -42,17 +42,17 @@ static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
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tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
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tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero,
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val, hex_new_value[rnum]);
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#if HEX_DEBUG
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/*
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* Do this so HELPER(debug_commit_end) will know
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*
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* Note that slot_mask indicates the value is not written
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* (i.e., slot was cancelled), so we create a true/false value before
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* or'ing with hex_reg_written[rnum].
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*/
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tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
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tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
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#endif
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if (HEX_DEBUG) {
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/*
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* Do this so HELPER(debug_commit_end) will know
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*
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* Note that slot_mask indicates the value is not written
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* (i.e., slot was cancelled), so we create a true/false value before
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* or'ing with hex_reg_written[rnum].
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*/
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tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
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tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
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}
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tcg_temp_free(zero);
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tcg_temp_free(slot_mask);
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@ -61,10 +61,10 @@ static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
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static inline void gen_log_reg_write(int rnum, TCGv val)
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{
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tcg_gen_mov_tl(hex_new_value[rnum], val);
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#if HEX_DEBUG
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/* Do this so HELPER(debug_commit_end) will know */
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tcg_gen_movi_tl(hex_reg_written[rnum], 1);
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#endif
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if (HEX_DEBUG) {
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/* Do this so HELPER(debug_commit_end) will know */
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tcg_gen_movi_tl(hex_reg_written[rnum], 1);
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}
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}
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static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot)
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@ -84,19 +84,19 @@ static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot)
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tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum + 1],
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slot_mask, zero,
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val32, hex_new_value[rnum + 1]);
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#if HEX_DEBUG
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/*
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* Do this so HELPER(debug_commit_end) will know
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*
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* Note that slot_mask indicates the value is not written
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* (i.e., slot was cancelled), so we create a true/false value before
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* or'ing with hex_reg_written[rnum].
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*/
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tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
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tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
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tcg_gen_or_tl(hex_reg_written[rnum + 1], hex_reg_written[rnum + 1],
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slot_mask);
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#endif
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if (HEX_DEBUG) {
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/*
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* Do this so HELPER(debug_commit_end) will know
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*
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* Note that slot_mask indicates the value is not written
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* (i.e., slot was cancelled), so we create a true/false value before
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* or'ing with hex_reg_written[rnum].
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*/
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tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
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tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
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tcg_gen_or_tl(hex_reg_written[rnum + 1], hex_reg_written[rnum + 1],
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slot_mask);
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}
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tcg_temp_free(val32);
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tcg_temp_free(zero);
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@ -107,17 +107,17 @@ static void gen_log_reg_write_pair(int rnum, TCGv_i64 val)
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{
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/* Low word */
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tcg_gen_extrl_i64_i32(hex_new_value[rnum], val);
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#if HEX_DEBUG
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/* Do this so HELPER(debug_commit_end) will know */
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tcg_gen_movi_tl(hex_reg_written[rnum], 1);
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#endif
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if (HEX_DEBUG) {
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/* Do this so HELPER(debug_commit_end) will know */
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tcg_gen_movi_tl(hex_reg_written[rnum], 1);
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}
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/* High word */
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tcg_gen_extrh_i64_i32(hex_new_value[rnum + 1], val);
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#if HEX_DEBUG
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/* Do this so HELPER(debug_commit_end) will know */
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tcg_gen_movi_tl(hex_reg_written[rnum + 1], 1);
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#endif
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if (HEX_DEBUG) {
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/* Do this so HELPER(debug_commit_end) will know */
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tcg_gen_movi_tl(hex_reg_written[rnum + 1], 1);
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}
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}
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static inline void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val)
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@ -19,11 +19,9 @@
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#include "helper_protos_generated.h.inc"
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DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_RETURN, noreturn, env, i32)
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#if HEX_DEBUG
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DEF_HELPER_1(debug_start_packet, void, env)
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DEF_HELPER_FLAGS_3(debug_check_store_width, TCG_CALL_NO_WG, void, env, int, int)
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DEF_HELPER_FLAGS_3(debug_commit_end, TCG_CALL_NO_WG, void, env, int, int)
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#endif
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DEF_HELPER_2(commit_store, void, env, int)
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DEF_HELPER_FLAGS_4(fcircadd, TCG_CALL_NO_RWG_SE, s32, s32, s32, s32, s32)
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@ -22,11 +22,12 @@
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* Change HEX_DEBUG to 1 to turn on debugging output
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*/
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#define HEX_DEBUG 0
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#if HEX_DEBUG
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#define HEX_DEBUG_LOG(...) qemu_log(__VA_ARGS__)
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#else
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#define HEX_DEBUG_LOG(...) do { } while (0)
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#endif
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#define HEX_DEBUG_LOG(...) \
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do { \
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if (HEX_DEBUG) { \
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qemu_log(__VA_ARGS__); \
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} \
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} while (0)
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int hexagon_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int hexagon_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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@ -56,10 +56,10 @@ static void log_reg_write(CPUHexagonState *env, int rnum,
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HEX_DEBUG_LOG("\n");
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env->new_value[rnum] = val;
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#if HEX_DEBUG
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/* Do this so HELPER(debug_commit_end) will know */
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env->reg_written[rnum] = 1;
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#endif
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if (HEX_DEBUG) {
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/* Do this so HELPER(debug_commit_end) will know */
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env->reg_written[rnum] = 1;
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}
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}
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static void log_pred_write(CPUHexagonState *env, int pnum, target_ulong val)
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@ -117,7 +117,6 @@ static void write_new_pc(CPUHexagonState *env, target_ulong addr)
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}
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}
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#if HEX_DEBUG
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/* Handy place to set a breakpoint */
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void HELPER(debug_start_packet)(CPUHexagonState *env)
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{
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@ -128,14 +127,12 @@ void HELPER(debug_start_packet)(CPUHexagonState *env)
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env->reg_written[i] = 0;
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}
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}
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#endif
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static int32_t new_pred_value(CPUHexagonState *env, int pnum)
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{
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return env->new_pred_value[pnum];
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}
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#if HEX_DEBUG
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/* Checks for bookkeeping errors between disassembly context and runtime */
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void HELPER(debug_check_store_width)(CPUHexagonState *env, int slot, int check)
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{
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@ -145,7 +142,6 @@ void HELPER(debug_check_store_width)(CPUHexagonState *env, int slot, int check)
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g_assert_not_reached();
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}
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}
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#endif
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void HELPER(commit_store)(CPUHexagonState *env, int slot_num)
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{
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@ -171,7 +167,6 @@ void HELPER(commit_store)(CPUHexagonState *env, int slot_num)
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}
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}
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#if HEX_DEBUG
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static void print_store(CPUHexagonState *env, int slot)
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{
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if (!(env->slot_cancelled & (1 << slot))) {
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@ -255,7 +250,6 @@ void HELPER(debug_commit_end)(CPUHexagonState *env, int has_st0, int has_st1)
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env->gpr[HEX_REG_QEMU_INSN_CNT]);
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}
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#endif
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static int32_t fcircadd_v4(int32_t RxV, int32_t offset, int32_t M, int32_t CS)
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{
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@ -35,9 +35,7 @@ TCGv hex_this_PC;
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TCGv hex_slot_cancelled;
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TCGv hex_branch_taken;
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TCGv hex_new_value[TOTAL_PER_THREAD_REGS];
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#if HEX_DEBUG
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TCGv hex_reg_written[TOTAL_PER_THREAD_REGS];
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#endif
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TCGv hex_new_pred_value[NUM_PREGS];
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TCGv hex_pred_written;
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TCGv hex_store_addr[STORES_MAX];
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@ -90,7 +88,6 @@ static void gen_exception_end_tb(DisasContext *ctx, int excp)
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}
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#if HEX_DEBUG
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#define PACKET_BUFFER_LEN 1028
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static void print_pkt(Packet *pkt)
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{
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@ -99,10 +96,12 @@ static void print_pkt(Packet *pkt)
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HEX_DEBUG_LOG("%s", buf->str);
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g_string_free(buf, true);
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}
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#define HEX_DEBUG_PRINT_PKT(pkt) print_pkt(pkt)
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#else
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#define HEX_DEBUG_PRINT_PKT(pkt) /* nothing */
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#endif
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#define HEX_DEBUG_PRINT_PKT(pkt) \
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do { \
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if (HEX_DEBUG) { \
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print_pkt(pkt); \
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} \
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} while (0)
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static int read_packet_words(CPUHexagonState *env, DisasContext *ctx,
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uint32_t words[])
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@ -179,11 +178,11 @@ static void gen_start_packet(DisasContext *ctx, Packet *pkt)
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tcg_gen_movi_tl(hex_pkt_has_store_s1, pkt->pkt_has_store_s1);
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ctx->s1_store_processed = false;
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#if HEX_DEBUG
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/* Handy place to set a breakpoint before the packet executes */
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gen_helper_debug_start_packet(cpu_env);
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tcg_gen_movi_tl(hex_this_PC, ctx->base.pc_next);
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#endif
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if (HEX_DEBUG) {
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/* Handy place to set a breakpoint before the packet executes */
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gen_helper_debug_start_packet(cpu_env);
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tcg_gen_movi_tl(hex_this_PC, ctx->base.pc_next);
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}
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/* Initialize the runtime state for packet semantics */
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if (need_pc(pkt)) {
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for (i = 0; i < ctx->preg_log_idx; i++) {
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int pred_num = ctx->preg_log[i];
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tcg_gen_mov_tl(hex_pred[pred_num], hex_new_pred_value[pred_num]);
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#if HEX_DEBUG
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/* Do this so HELPER(debug_commit_end) will know */
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tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pred_num);
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#endif
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if (HEX_DEBUG) {
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/* Do this so HELPER(debug_commit_end) will know */
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tcg_gen_ori_tl(hex_pred_written, hex_pred_written,
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1 << pred_num);
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}
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}
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}
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@ -322,13 +322,13 @@ static void gen_pred_writes(DisasContext *ctx, Packet *pkt)
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static void gen_check_store_width(DisasContext *ctx, int slot_num)
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{
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#if HEX_DEBUG
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TCGv slot = tcg_const_tl(slot_num);
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TCGv check = tcg_const_tl(ctx->store_width[slot_num]);
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gen_helper_debug_check_store_width(cpu_env, slot, check);
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tcg_temp_free(slot);
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tcg_temp_free(check);
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#endif
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if (HEX_DEBUG) {
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TCGv slot = tcg_const_tl(slot_num);
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TCGv check = tcg_const_tl(ctx->store_width[slot_num]);
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gen_helper_debug_check_store_width(cpu_env, slot, check);
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tcg_temp_free(slot);
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tcg_temp_free(check);
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}
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}
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static bool slot_is_predicated(Packet *pkt, int slot_num)
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@ -482,8 +482,7 @@ static void gen_commit_packet(DisasContext *ctx, Packet *pkt)
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process_store_log(ctx, pkt);
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process_dczeroa(ctx, pkt);
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update_exec_counters(ctx, pkt);
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#if HEX_DEBUG
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{
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if (HEX_DEBUG) {
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TCGv has_st0 =
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tcg_const_tl(pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa);
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TCGv has_st1 =
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@ -495,7 +494,6 @@ static void gen_commit_packet(DisasContext *ctx, Packet *pkt)
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tcg_temp_free(has_st0);
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tcg_temp_free(has_st1);
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}
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#endif
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if (pkt->pkt_has_cof) {
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gen_end_tb(ctx);
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#define NAME_LEN 64
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static char new_value_names[TOTAL_PER_THREAD_REGS][NAME_LEN];
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#if HEX_DEBUG
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static char reg_written_names[TOTAL_PER_THREAD_REGS][NAME_LEN];
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#endif
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static char new_pred_value_names[NUM_PREGS][NAME_LEN];
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static char store_addr_names[STORES_MAX][NAME_LEN];
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static char store_width_names[STORES_MAX][NAME_LEN];
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@ -670,11 +666,11 @@ void hexagon_translate_init(void)
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opcode_init();
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#if HEX_DEBUG
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if (!qemu_logfile) {
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qemu_set_log(qemu_loglevel);
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if (HEX_DEBUG) {
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if (!qemu_logfile) {
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qemu_set_log(qemu_loglevel);
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}
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}
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#endif
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for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) {
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hex_gpr[i] = tcg_global_mem_new(cpu_env,
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@ -686,13 +682,13 @@ void hexagon_translate_init(void)
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offsetof(CPUHexagonState, new_value[i]),
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new_value_names[i]);
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#if HEX_DEBUG
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snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s",
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hexagon_regnames[i]);
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hex_reg_written[i] = tcg_global_mem_new(cpu_env,
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offsetof(CPUHexagonState, reg_written[i]),
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reg_written_names[i]);
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#endif
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if (HEX_DEBUG) {
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snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s",
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hexagon_regnames[i]);
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hex_reg_written[i] = tcg_global_mem_new(cpu_env,
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offsetof(CPUHexagonState, reg_written[i]),
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reg_written_names[i]);
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}
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}
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for (i = 0; i < NUM_PREGS; i++) {
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hex_pred[i] = tcg_global_mem_new(cpu_env,
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@ -41,11 +41,9 @@ typedef struct DisasContext {
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static inline void ctx_log_reg_write(DisasContext *ctx, int rnum)
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{
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#if HEX_DEBUG
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if (test_bit(rnum, ctx->regs_written)) {
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HEX_DEBUG_LOG("WARNING: Multiple writes to r%d\n", rnum);
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}
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#endif
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ctx->reg_log[ctx->reg_log_idx] = rnum;
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ctx->reg_log_idx++;
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set_bit(rnum, ctx->regs_written);
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