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hw/intc: riscv_aclint: Add reset function of ACLINT devices
This commit implements reset function of all ACLINT devices. ACLINT device reset will clear MTIME and MSIP register to 0. Depend on RISC-V ACLINT spec v1.0-rc4: https://github.com/riscv/riscv-aclint/blob/v1.0-rc4/riscv-aclint.adoc Signed-off-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220420080901.14655-5-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -293,11 +293,29 @@ static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp)
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}
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}
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}
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}
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static void riscv_aclint_mtimer_reset_enter(Object *obj, ResetType type)
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{
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/*
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* According to RISC-V ACLINT spec:
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* - On MTIMER device reset, the MTIME register is cleared to zero.
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* - On MTIMER device reset, the MTIMECMP registers are in unknown state.
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*/
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RISCVAclintMTimerState *mtimer = RISCV_ACLINT_MTIMER(obj);
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/*
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* Clear mtime register by writing to 0 it.
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* Pending mtime interrupts will also be cleared at the same time.
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*/
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riscv_aclint_mtimer_write(mtimer, mtimer->time_base, 0, 8);
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}
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static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data)
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static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data)
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{
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = riscv_aclint_mtimer_realize;
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dc->realize = riscv_aclint_mtimer_realize;
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device_class_set_props(dc, riscv_aclint_mtimer_properties);
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device_class_set_props(dc, riscv_aclint_mtimer_properties);
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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rc->phases.enter = riscv_aclint_mtimer_reset_enter;
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}
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}
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static const TypeInfo riscv_aclint_mtimer_info = {
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static const TypeInfo riscv_aclint_mtimer_info = {
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@ -452,11 +470,32 @@ static void riscv_aclint_swi_realize(DeviceState *dev, Error **errp)
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}
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}
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}
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}
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static void riscv_aclint_swi_reset_enter(Object *obj, ResetType type)
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{
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/*
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* According to RISC-V ACLINT spec:
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* - On MSWI device reset, each MSIP register is cleared to zero.
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*
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* p.s. SSWI device reset does nothing since SETSIP register always reads 0.
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*/
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RISCVAclintSwiState *swi = RISCV_ACLINT_SWI(obj);
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int i;
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if (!swi->sswi) {
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for (i = 0; i < swi->num_harts; i++) {
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/* Clear MSIP registers by lowering software interrupts. */
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qemu_irq_lower(swi->soft_irqs[i]);
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}
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}
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}
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static void riscv_aclint_swi_class_init(ObjectClass *klass, void *data)
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static void riscv_aclint_swi_class_init(ObjectClass *klass, void *data)
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{
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = riscv_aclint_swi_realize;
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dc->realize = riscv_aclint_swi_realize;
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device_class_set_props(dc, riscv_aclint_swi_properties);
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device_class_set_props(dc, riscv_aclint_swi_properties);
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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rc->phases.enter = riscv_aclint_swi_reset_enter;
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}
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}
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static const TypeInfo riscv_aclint_swi_info = {
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static const TypeInfo riscv_aclint_swi_info = {
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