mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-10-14 23:13:30 +00:00
target-arm queue:
* take HSTR traps of cp15 accesses to EL2, not EL1 * docs: sbsa: update specs, add dt note * hw/intc/arm_gicv3: ICC_HPPIR* return SPURIOUS if int group is disabled * tests/qtest: Fix STM32L4x5 GPIO test on 32-bit * raspi4b: Reduce RAM to 1Gb on 32-bit hosts -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmYL3J8ZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3lL9D/9ayKF76MKs+oK8+uHTOLPb Mk71K1apgFnkzC7v9xuI76M6SzZpcKslUbieucDhkDLdVuZvlV3eUcwQGbNWu9fx PCkx7RmD54o+nlGxacZx4wGDfgu9j3maCVik048WxNoHb03NPahfHIb/GFRyHgt/ TTjeqfAX7GDbHzMiGuaEJi5dLuAP0/imLt7pooJv4JRDX3CMY+tzlclU4ySMBr+S 0fs5oi6kZMayM8iolpSrPDQy/N3jZJpd5pNPPIcsnL5DEJHKodHbD11+Zetb1tQ7 Tyw+x+hUb8Yx2WADVBaihYnbvakUVLt7ZzdgDENV534O/1Vmabzt14CBGTwq4faQ 8Hbc4e/ulhsOUlaxCDKTCuCKDW7sub7UelSz7mX6dAwcjvEi/L99dkP1wSpl0W04 3uTQyjDrfCOVNJ/FMYLRp5VkjwUVacbs3u3Tpe2bgRMI+hxnKZjtIMIY09q3l7em JrPOsiiJlVzngcQko1K0cor3p5W43HIhLUlh0RqJL/CsVhXFfHShAJowK31vGnNp ITklT5CWKMmogHTJycQieemhwwKaALgCUBC9TrcD1dTJe/GksYXVg6Fit7IJttBI zsPMM21Namtr1tKsV71xgtpDrkiWZkeFRpo/GrEf50bX1Mx7Dc8D/ons2RS0G2vo S13Dyt6GBtzS9M8rKX2fsQ== =rYVb -----END PGP SIGNATURE----- Merge tag 'pull-target-arm-20240402' of https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * take HSTR traps of cp15 accesses to EL2, not EL1 * docs: sbsa: update specs, add dt note * hw/intc/arm_gicv3: ICC_HPPIR* return SPURIOUS if int group is disabled * tests/qtest: Fix STM32L4x5 GPIO test on 32-bit * raspi4b: Reduce RAM to 1Gb on 32-bit hosts # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmYL3J8ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3lL9D/9ayKF76MKs+oK8+uHTOLPb # Mk71K1apgFnkzC7v9xuI76M6SzZpcKslUbieucDhkDLdVuZvlV3eUcwQGbNWu9fx # PCkx7RmD54o+nlGxacZx4wGDfgu9j3maCVik048WxNoHb03NPahfHIb/GFRyHgt/ # TTjeqfAX7GDbHzMiGuaEJi5dLuAP0/imLt7pooJv4JRDX3CMY+tzlclU4ySMBr+S # 0fs5oi6kZMayM8iolpSrPDQy/N3jZJpd5pNPPIcsnL5DEJHKodHbD11+Zetb1tQ7 # Tyw+x+hUb8Yx2WADVBaihYnbvakUVLt7ZzdgDENV534O/1Vmabzt14CBGTwq4faQ # 8Hbc4e/ulhsOUlaxCDKTCuCKDW7sub7UelSz7mX6dAwcjvEi/L99dkP1wSpl0W04 # 3uTQyjDrfCOVNJ/FMYLRp5VkjwUVacbs3u3Tpe2bgRMI+hxnKZjtIMIY09q3l7em # JrPOsiiJlVzngcQko1K0cor3p5W43HIhLUlh0RqJL/CsVhXFfHShAJowK31vGnNp # ITklT5CWKMmogHTJycQieemhwwKaALgCUBC9TrcD1dTJe/GksYXVg6Fit7IJttBI # zsPMM21Namtr1tKsV71xgtpDrkiWZkeFRpo/GrEf50bX1Mx7Dc8D/ons2RS0G2vo # S13Dyt6GBtzS9M8rKX2fsQ== # =rYVb # -----END PGP SIGNATURE----- # gpg: Signature made Tue 02 Apr 2024 11:23:27 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20240402' of https://git.linaro.org/people/pmaydell/qemu-arm: raspi4b: Reduce RAM to 1Gb on 32-bit hosts tests/qtest: Fix STM32L4x5 GPIO test on 32-bit hw/intc/arm_gicv3: ICC_HPPIR* return SPURIOUS if int group is disabled docs: sbsa: update specs, add dt note target/arm: take HSTR traps of cp15 accesses to EL2, not EL1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
7fcf7575f3
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@ -1,12 +1,16 @@
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Arm Server Base System Architecture Reference board (``sbsa-ref``)
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==================================================================
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While the ``virt`` board is a generic board platform that doesn't match
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any real hardware the ``sbsa-ref`` board intends to look like real
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hardware. The `Server Base System Architecture
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<https://developer.arm.com/documentation/den0029/latest>`_ defines a
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minimum base line of hardware support and importantly how the firmware
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reports that to any operating system.
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The ``sbsa-ref`` board intends to look like real hardware (while the ``virt``
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board is a generic board platform that doesn't match any real hardware).
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The hardware part is defined by two specifications:
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- `Base System Architecture <https://developer.arm.com/documentation/den0094/>`__ (BSA)
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- `Server Base System Architecture <https://developer.arm.com/documentation/den0029/>`__ (SBSA)
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The `Arm Base Boot Requirements <https://developer.arm.com/documentation/den0044/>`__ (BBR)
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specification defines how the firmware reports that to any operating system.
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It is intended to be a machine for developing firmware and testing
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standards compliance with operating systems.
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@ -35,16 +39,29 @@ includes both internal hardware and parts affected by the qemu command line
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(i.e. CPUs and memory). As a result it must have a firmware specifically built
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to expect a certain hardware layout (as you would in a real machine).
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Note
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''''
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QEMU provides the guest EL3 firmware with minimal information about hardware
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platform using minimalistic devicetree. This is not a Linux devicetree. It is
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not even a firmware devicetree.
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It is information passed from QEMU to describe the information a hardware
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platform would have other mechanisms to discover at runtime, that are affected
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by the QEMU command line.
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Ultimately this devicetree may be replaced by IPC calls to an emulated SCP.
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DeviceTree information
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''''''''''''''''''''''
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The devicetree provided by the board model to the firmware is not intended
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to be a complete compliant DT. It currently reports:
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The devicetree reports:
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- CPUs
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- memory
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- platform version
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- GIC addresses
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- NUMA node id for CPUs and memory
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Platform version
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''''''''''''''''
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@ -70,4 +87,4 @@ Platform version changes:
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GIC ITS information is present in devicetree.
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0.3
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The USB controller is an XHCI device, not EHCI
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The USB controller is an XHCI device, not EHCI.
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@ -112,7 +112,11 @@ static void raspi4b_machine_class_init(ObjectClass *oc, void *data)
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MachineClass *mc = MACHINE_CLASS(oc);
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RaspiBaseMachineClass *rmc = RASPI_BASE_MACHINE_CLASS(oc);
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#if HOST_LONG_BITS == 32
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rmc->board_rev = 0xa03111; /* Revision 1.1, 1 Gb RAM */
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#else
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rmc->board_rev = 0xb03115; /* Revision 1.5, 2 Gb RAM */
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#endif
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raspi_machine_class_common_init(mc, rmc->board_rev);
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mc->init = raspi4b_machine_init;
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}
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@ -1067,7 +1067,7 @@ static uint64_t icc_hppir0_value(GICv3CPUState *cs, CPUARMState *env)
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*/
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bool irq_is_secure;
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if (cs->hppi.prio == 0xff) {
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if (icc_no_enabled_hppi(cs)) {
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return INTID_SPURIOUS;
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}
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@ -1104,7 +1104,7 @@ static uint64_t icc_hppir1_value(GICv3CPUState *cs, CPUARMState *env)
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*/
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bool irq_is_secure;
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if (cs->hppi.prio == 0xff) {
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if (icc_no_enabled_hppi(cs)) {
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return INTID_SPURIOUS;
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}
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@ -4585,7 +4585,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
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tcg_gen_andi_i32(t, t, 1u << maskbit);
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tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label);
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gen_exception_insn(s, 0, EXCP_UDEF, syndrome);
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gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2);
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/*
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* gen_exception_insn() will set is_jmp to DISAS_NORETURN,
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* but since we're conditionally branching over it, we want
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@ -76,6 +76,17 @@ const uint32_t idr_reset[NUM_GPIOS] = {
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0x00000000
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};
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#define PIN_MASK 0xF
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#define GPIO_ADDR_MASK (~(GPIO_SIZE - 1))
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static inline void *test_data(uint32_t gpio_addr, uint8_t pin)
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{
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return (void *)(uintptr_t)((gpio_addr & GPIO_ADDR_MASK) | (pin & PIN_MASK));
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}
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#define test_gpio_addr(data) ((uintptr_t)(data) & GPIO_ADDR_MASK)
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#define test_pin(data) ((uintptr_t)(data) & PIN_MASK)
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static uint32_t gpio_readl(unsigned int gpio, unsigned int offset)
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{
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return readl(gpio + offset);
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@ -269,8 +280,8 @@ static void test_gpio_output_mode(const void *data)
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* Additionally, it checks that values written to ODR
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* when not in output mode are stored and not discarded.
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*/
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unsigned int pin = ((uint64_t)data) & 0xF;
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uint32_t gpio = ((uint64_t)data) >> 32;
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unsigned int pin = test_pin(data);
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uint32_t gpio = test_gpio_addr(data);
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unsigned int gpio_id = get_gpio_id(gpio);
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qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
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@ -304,8 +315,8 @@ static void test_gpio_input_mode(const void *data)
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* corresponding GPIO line high/low : it should set the
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* right bit in IDR and send an irq to syscfg.
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*/
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unsigned int pin = ((uint64_t)data) & 0xF;
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uint32_t gpio = ((uint64_t)data) >> 32;
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unsigned int pin = test_pin(data);
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uint32_t gpio = test_gpio_addr(data);
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unsigned int gpio_id = get_gpio_id(gpio);
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qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
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@ -333,8 +344,8 @@ static void test_pull_up_pull_down(const void *data)
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* Test that a floating pin with pull-up sets the pin
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* high and vice-versa.
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*/
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unsigned int pin = ((uint64_t)data) & 0xF;
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uint32_t gpio = ((uint64_t)data) >> 32;
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unsigned int pin = test_pin(data);
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uint32_t gpio = test_gpio_addr(data);
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unsigned int gpio_id = get_gpio_id(gpio);
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qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
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@ -363,8 +374,8 @@ static void test_push_pull(const void *data)
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* disconnects the pin, that the pin can't be set or reset
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* externally afterwards.
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*/
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unsigned int pin = ((uint64_t)data) & 0xF;
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uint32_t gpio = ((uint64_t)data) >> 32;
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unsigned int pin = test_pin(data);
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uint32_t gpio = test_gpio_addr(data);
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uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
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qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
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@ -410,8 +421,8 @@ static void test_open_drain(const void *data)
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* However a pin set low externally shouldn't be disconnected,
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* and it can be set low externally when in open-drain mode.
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*/
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unsigned int pin = ((uint64_t)data) & 0xF;
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uint32_t gpio = ((uint64_t)data) >> 32;
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unsigned int pin = test_pin(data);
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uint32_t gpio = test_gpio_addr(data);
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uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
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qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
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@ -466,8 +477,8 @@ static void test_bsrr_brr(const void *data)
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* has the desired effect on ODR.
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* In BSRR, BSx has priority over BRx.
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*/
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unsigned int pin = ((uint64_t)data) & 0xF;
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uint32_t gpio = ((uint64_t)data) >> 32;
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unsigned int pin = test_pin(data);
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uint32_t gpio = test_gpio_addr(data);
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gpio_writel(gpio, BSRR, (1 << pin));
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g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
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@ -507,40 +518,40 @@ int main(int argc, char **argv)
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* is problematic since the pin was already high.
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*/
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qtest_add_data_func("stm32l4x5/gpio/test_gpioc5_output_mode",
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(void *)((uint64_t)GPIO_C << 32 | 5),
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test_data(GPIO_C, 5),
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test_gpio_output_mode);
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qtest_add_data_func("stm32l4x5/gpio/test_gpioh3_output_mode",
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(void *)((uint64_t)GPIO_H << 32 | 3),
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test_data(GPIO_H, 3),
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test_gpio_output_mode);
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qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode1",
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(void *)((uint64_t)GPIO_D << 32 | 6),
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test_data(GPIO_D, 6),
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test_gpio_input_mode);
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qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode2",
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(void *)((uint64_t)GPIO_C << 32 | 10),
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test_data(GPIO_C, 10),
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test_gpio_input_mode);
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qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down1",
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(void *)((uint64_t)GPIO_B << 32 | 5),
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test_data(GPIO_B, 5),
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test_pull_up_pull_down);
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qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down2",
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(void *)((uint64_t)GPIO_F << 32 | 1),
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test_data(GPIO_F, 1),
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test_pull_up_pull_down);
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qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull1",
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(void *)((uint64_t)GPIO_G << 32 | 6),
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test_data(GPIO_G, 6),
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test_push_pull);
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qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull2",
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(void *)((uint64_t)GPIO_H << 32 | 3),
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test_data(GPIO_H, 3),
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test_push_pull);
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qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain1",
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(void *)((uint64_t)GPIO_C << 32 | 4),
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test_data(GPIO_C, 4),
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test_open_drain);
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qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain2",
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(void *)((uint64_t)GPIO_E << 32 | 11),
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test_data(GPIO_E, 11),
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test_open_drain);
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qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr1",
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(void *)((uint64_t)GPIO_A << 32 | 12),
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test_data(GPIO_A, 12),
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test_bsrr_brr);
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qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr2",
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(void *)((uint64_t)GPIO_D << 32 | 0),
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test_data(GPIO_D, 0),
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test_bsrr_brr);
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qtest_start("-machine b-l475e-iot01a");
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|
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