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tcg/tci: Merge INDEX_op_ld8u_{i32,i64}
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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20
tcg/tci.c
20
tcg/tci.c
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@ -455,6 +455,18 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
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# define qemu_st_beq(X) stq_be_p(g2h(taddr), X)
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#endif
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#if TCG_TARGET_REG_BITS == 64
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# define CASE_32_64(x) \
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case glue(glue(INDEX_op_, x), _i64): \
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case glue(glue(INDEX_op_, x), _i32):
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# define CASE_64(x) \
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case glue(glue(INDEX_op_, x), _i64):
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#else
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# define CASE_32_64(x) \
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case glue(glue(INDEX_op_, x), _i32):
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# define CASE_64(x)
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#endif
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/* Interpret pseudo code in tb. */
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/*
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* Disable CFI checks.
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@ -569,7 +581,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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/* Load/store operations (32 bit). */
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case INDEX_op_ld8u_i32:
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CASE_32_64(ld8u)
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t0 = *tb_ptr++;
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t1 = tci_read_r(regs, &tb_ptr);
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t2 = tci_read_s32(&tb_ptr);
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@ -843,12 +855,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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/* Load/store operations (64 bit). */
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case INDEX_op_ld8u_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_r(regs, &tb_ptr);
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t2 = tci_read_s32(&tb_ptr);
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tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2));
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break;
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case INDEX_op_ld8s_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_r(regs, &tb_ptr);
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