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target-i386: Perform set/reset_inhibit_irq inline
With helpers that can be reused for other things. Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -383,13 +383,3 @@ void helper_sti_vm(CPUX86State *env)
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}
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}
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#endif
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void helper_set_inhibit_irq(CPUX86State *env)
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{
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env->hflags |= HF_INHIBIT_IRQ_MASK;
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}
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void helper_reset_inhibit_irq(CPUX86State *env)
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{
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env->hflags &= ~HF_INHIBIT_IRQ_MASK;
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}
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@ -62,8 +62,6 @@ DEF_HELPER_1(cli, void, env)
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DEF_HELPER_1(sti, void, env)
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DEF_HELPER_1(clac, void, env)
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DEF_HELPER_1(stac, void, env)
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DEF_HELPER_1(set_inhibit_irq, void, env)
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DEF_HELPER_1(reset_inhibit_irq, void, env)
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DEF_HELPER_3(boundw, void, env, tl, int)
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DEF_HELPER_3(boundl, void, env, tl, int)
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DEF_HELPER_1(rsm, void, env)
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@ -2391,14 +2391,36 @@ static void gen_debug(DisasContext *s, target_ulong cur_eip)
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s->is_jmp = DISAS_TB_JUMP;
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}
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static void gen_set_hflag(DisasContext *s, uint32_t mask)
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{
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if ((s->flags & mask) == 0) {
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TCGv_i32 t = tcg_temp_new_i32();
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tcg_gen_ld_i32(t, cpu_env, offsetof(CPUX86State, hflags));
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tcg_gen_ori_i32(t, t, mask);
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tcg_gen_st_i32(t, cpu_env, offsetof(CPUX86State, hflags));
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tcg_temp_free_i32(t);
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s->flags |= mask;
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}
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}
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static void gen_reset_hflag(DisasContext *s, uint32_t mask)
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{
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if (s->flags & mask) {
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TCGv_i32 t = tcg_temp_new_i32();
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tcg_gen_ld_i32(t, cpu_env, offsetof(CPUX86State, hflags));
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tcg_gen_andi_i32(t, t, ~mask);
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tcg_gen_st_i32(t, cpu_env, offsetof(CPUX86State, hflags));
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tcg_temp_free_i32(t);
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s->flags &= ~mask;
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}
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}
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/* generate a generic end of block. Trace exception is also generated
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if needed */
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static void gen_eob(DisasContext *s)
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{
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gen_update_cc_op(s);
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if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
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gen_helper_reset_inhibit_irq(cpu_env);
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}
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gen_reset_hflag(s, HF_INHIBIT_IRQ_MASK);
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if (s->tb->flags & HF_RF_MASK) {
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gen_helper_reset_rf(cpu_env);
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}
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@ -5147,8 +5169,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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/* if reg == SS, inhibit interrupts/trace. */
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/* If several instructions disable interrupts, only the
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_first_ does it */
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if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
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gen_helper_set_inhibit_irq(cpu_env);
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gen_set_hflag(s, HF_INHIBIT_IRQ_MASK);
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s->tf = 0;
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}
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if (s->is_jmp) {
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@ -5215,8 +5236,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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/* if reg == SS, inhibit interrupts/trace */
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/* If several instructions disable interrupts, only the
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_first_ does it */
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if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
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gen_helper_set_inhibit_irq(cpu_env);
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gen_set_hflag(s, HF_INHIBIT_IRQ_MASK);
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s->tf = 0;
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}
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if (s->is_jmp) {
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@ -6752,8 +6772,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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/* interruptions are enabled only the first insn after sti */
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/* If several instructions disable interrupts, only the
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_first_ does it */
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if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
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gen_helper_set_inhibit_irq(cpu_env);
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gen_set_hflag(s, HF_INHIBIT_IRQ_MASK);
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/* give a chance to handle pending irqs */
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gen_jmp_im(s->pc - s->cs_base);
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gen_eob(s);
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