mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-11-05 20:35:44 +00:00
quick and dirty CMOS irq emulation (windows install uses it) - emm386 keyboard fix (need a better way...) - better serial emulation (windows install uses it) - LDT and TR caches init fix
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@461 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
4ce900b44c
commit
7dea1da4ae
1 changed files with 118 additions and 12 deletions
130
vl.c
130
vl.c
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@ -61,6 +61,8 @@
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/* output Bochs bios info messages */
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//#define DEBUG_BIOS
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//#define DEBUG_CMOS
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/* debug PIC */
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//#define DEBUG_PIC
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@ -73,6 +75,8 @@
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/* debug PC keyboard : only mouse */
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//#define DEBUG_MOUSE
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//#define DEBUG_SERIAL
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#define PHYS_RAM_BASE 0xac000000
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#define PHYS_RAM_MAX_SIZE (256 * 1024 * 1024)
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@ -197,7 +201,8 @@ struct __attribute__ ((packed)) linux_params {
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#define KERNEL_CS 0x10
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#define KERNEL_DS 0x18
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#define MAX_IOPORTS 4096
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/* XXX: use a two level table to limit memory usage */
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#define MAX_IOPORTS 65536
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static const char *bios_dir = CONFIG_QEMU_SHAREDIR;
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char phys_ram_file[1024];
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@ -461,6 +466,39 @@ void cmos_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data)
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{
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if (addr == 0x70) {
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cmos_index = data & 0x7f;
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} else {
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#ifdef DEBUG_CMOS
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printf("cmos: write index=0x%02x val=0x%02x\n",
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cmos_index, data);
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#endif
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switch(addr) {
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case RTC_SECONDS_ALARM:
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case RTC_MINUTES_ALARM:
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case RTC_HOURS_ALARM:
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/* XXX: not supported */
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cmos_data[cmos_index] = data;
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break;
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case RTC_SECONDS:
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case RTC_MINUTES:
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case RTC_HOURS:
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case RTC_DAY_OF_WEEK:
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case RTC_DAY_OF_MONTH:
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case RTC_MONTH:
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case RTC_YEAR:
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cmos_data[cmos_index] = data;
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break;
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case RTC_REG_A:
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case RTC_REG_B:
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cmos_data[cmos_index] = data;
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break;
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case RTC_REG_C:
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case RTC_REG_D:
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/* cannot write to them */
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break;
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default:
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cmos_data[cmos_index] = data;
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break;
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}
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}
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}
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@ -471,13 +509,22 @@ uint32_t cmos_ioport_read(CPUX86State *env, uint32_t addr)
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if (addr == 0x70) {
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return 0xff;
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} else {
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/* toggle update-in-progress bit for Linux (same hack as
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plex86) */
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ret = cmos_data[cmos_index];
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if (cmos_index == RTC_REG_A)
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switch(cmos_index) {
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case RTC_REG_A:
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/* toggle update-in-progress bit for Linux (same hack as
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plex86) */
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cmos_data[RTC_REG_A] ^= 0x80;
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else if (cmos_index == RTC_REG_C)
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break;
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case RTC_REG_C:
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pic_set_irq(8, 0);
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cmos_data[RTC_REG_C] = 0x00;
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break;
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}
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#ifdef DEBUG_CMOS
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printf("cmos: read index=0x%02x val=0x%02x\n",
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cmos_index, ret);
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#endif
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return ret;
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}
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}
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@ -675,7 +722,7 @@ int cpu_x86_get_pic_interrupt(CPUX86State *env)
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irq,
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(double)(cpu_get_ticks() - irq_time[irq]) * 1000000.0 / ticks_per_sec);
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#endif
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#ifdef DEBUG_PIC
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#if defined(DEBUG_PIC)
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printf("pic_interrupt: irq=%d\n", irq);
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#endif
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@ -1191,6 +1238,28 @@ void pit_init(void)
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
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/*
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* These are the definitions for the Modem Control Register
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*/
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#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
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#define UART_MCR_OUT2 0x08 /* Out2 complement */
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#define UART_MCR_OUT1 0x04 /* Out1 complement */
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#define UART_MCR_RTS 0x02 /* RTS complement */
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#define UART_MCR_DTR 0x01 /* DTR complement */
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/*
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* These are the definitions for the Modem Status Register
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*/
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#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
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#define UART_MSR_RI 0x40 /* Ring Indicator */
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#define UART_MSR_DSR 0x20 /* Data Set Ready */
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#define UART_MSR_CTS 0x10 /* Clear to Send */
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#define UART_MSR_DDCD 0x08 /* Delta DCD */
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#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
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#define UART_MSR_DDSR 0x02 /* Delta DSR */
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#define UART_MSR_DCTS 0x01 /* Delta CTS */
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#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
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#define UART_LSR_TEMT 0x40 /* Transmitter empty */
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#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
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#define UART_LSR_BI 0x10 /* Break interrupt indicator */
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@ -1209,6 +1278,9 @@ typedef struct SerialState {
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uint8_t lsr; /* read only */
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uint8_t msr;
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uint8_t scr;
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/* NOTE: this hidden state is necessary for tx irq generation as
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it can be reset while reading iir */
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int thr_ipending;
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} SerialState;
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SerialState serial_ports[1];
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@ -1219,7 +1291,7 @@ void serial_update_irq(void)
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if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
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s->iir = UART_IIR_RDI;
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} else if ((s->lsr & UART_LSR_THRE) && (s->ier & UART_IER_THRI)) {
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} else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
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s->iir = UART_IIR_THRI;
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} else {
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s->iir = UART_IIR_NO_INT;
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@ -1238,12 +1310,16 @@ void serial_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
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int ret;
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addr &= 7;
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#ifdef DEBUG_SERIAL
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printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
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#endif
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switch(addr) {
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default:
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case 0:
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if (s->lcr & UART_LCR_DLAB) {
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s->divider = (s->divider & 0xff00) | val;
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} else {
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s->thr_ipending = 0;
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s->lsr &= ~UART_LSR_THRE;
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serial_update_irq();
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@ -1251,6 +1327,7 @@ void serial_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
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do {
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ret = write(1, &ch, 1);
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} while (ret != 1);
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s->thr_ipending = 1;
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s->lsr |= UART_LSR_THRE;
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s->lsr |= UART_LSR_TEMT;
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serial_update_irq();
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@ -1309,6 +1386,10 @@ uint32_t serial_ioport_read(CPUX86State *env, uint32_t addr)
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break;
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case 2:
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ret = s->iir;
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/* reset THR pending bit */
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if ((ret & 0x7) == UART_IIR_THRI)
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s->thr_ipending = 0;
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serial_update_irq();
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break;
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case 3:
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ret = s->lcr;
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@ -1320,12 +1401,23 @@ uint32_t serial_ioport_read(CPUX86State *env, uint32_t addr)
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ret = s->lsr;
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break;
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case 6:
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ret = s->msr;
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if (s->mcr & UART_MCR_LOOP) {
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/* in loopback, the modem output pins are connected to the
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inputs */
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ret = (s->mcr & 0x0c) << 4;
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ret |= (s->mcr & 0x02) << 3;
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ret |= (s->mcr & 0x01) << 5;
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} else {
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ret = s->msr;
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}
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break;
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case 7:
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ret = s->scr;
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break;
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}
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#ifdef DEBUG_SERIAL
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printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
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#endif
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return ret;
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}
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@ -1388,7 +1480,8 @@ void serial_init(void)
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SerialState *s = &serial_ports[0];
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s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
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s->iir = UART_IIR_NO_INT;
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register_ioport_write(0x3f8, 8, serial_ioport_write, 1);
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register_ioport_read(0x3f8, 8, serial_ioport_read, 1);
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}
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@ -2108,14 +2201,20 @@ uint32_t kbd_read_data(CPUX86State *env, uint32_t addr)
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{
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KBDState *s = &kbd_state;
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KBDQueue *q;
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int val;
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int val, index;
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q = &s->queues[0]; /* first check KBD data */
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if (q->count == 0)
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q = &s->queues[1]; /* then check AUX data */
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if (q->count == 0) {
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/* XXX: return something else ? */
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val = 0;
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/* NOTE: if no data left, we return the last keyboard one
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(needed for EMM386) */
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/* XXX: need a timer to do things correctly */
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q = &s->queues[0];
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index = q->rptr - 1;
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if (index < 0)
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index = KBD_QUEUE_SIZE - 1;
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val = q->data[index];
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} else {
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val = q->data[q->rptr];
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if (++q->rptr == KBD_QUEUE_SIZE)
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@ -2730,6 +2829,10 @@ int main_loop(void *opaque)
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pic_set_irq(0, 1);
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pic_set_irq(0, 0);
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timer_irq_pending = 0;
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/* XXX: RTC test */
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if (cmos_data[RTC_REG_B] & 0x40) {
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pic_set_irq(8, 1);
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}
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}
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/* VGA */
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@ -3116,6 +3219,9 @@ int main(int argc, char **argv)
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env->idt.limit = 0xffff;
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env->gdt.limit = 0xffff;
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env->ldt.limit = 0xffff;
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env->ldt.flags = DESC_P_MASK;
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env->tr.limit = 0xffff;
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env->tr.flags = DESC_P_MASK;
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/* not correct (CS base=0xffff0000) */
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cpu_x86_load_seg_cache(env, R_CS, 0xf000, (uint8_t *)0x000f0000, 0xffff, 0);
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