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https://gitlab.com/qemu-project/qemu
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target-mips: add Config5.FRE support allowing Status.FR=0 emulation
This relatively small architectural feature adds the following:
FIR.FREP: Read-only. If FREP=1, then Config5.FRE and Config5.UFE are
available.
Config5.FRE: When enabled all single-precision FP arithmetic instructions,
LWC1/LWXC1/MTC1, SWC1/SWXC1/MFC1 cause a Reserved Instructions
exception.
Config5.UFE: Allows user to write/read Config5.FRE using CTC1/CFC1
instructions.
Enable the feature in MIPS64R6-generic CPU.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
Leon Alrae
parent
eab9944c78
commit
7c979afd11
4 changed files with 208 additions and 156 deletions
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@ -100,6 +100,7 @@ struct CPUMIPSFPUContext {
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float_status fp_status;
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/* fpu implementation/revision register (fir) */
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uint32_t fcr0;
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#define FCR0_FREP 29
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#define FCR0_UFRP 28
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#define FCR0_F64 22
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#define FCR0_L 21
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@ -462,6 +463,8 @@ struct CPUMIPSState {
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#define CP0C5_CV 29
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#define CP0C5_EVA 28
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#define CP0C5_MSAEn 27
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#define CP0C5_UFE 9
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#define CP0C5_FRE 8
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#define CP0C5_SBRI 6
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#define CP0C5_UFR 2
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#define CP0C5_NFExists 0
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@ -514,7 +517,7 @@ struct CPUMIPSState {
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#define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
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uint32_t hflags; /* CPU State */
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/* TMASK defines different execution modes */
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#define MIPS_HFLAG_TMASK 0x15807FF
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#define MIPS_HFLAG_TMASK 0x35807FF
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#define MIPS_HFLAG_MODE 0x00007 /* execution modes */
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/* The KSU flags must be the lowest bits in hflags. The flag order
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must be the same as defined for CP0 Status. This allows to use
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@ -561,6 +564,7 @@ struct CPUMIPSState {
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#define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */
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#define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */
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#define MIPS_HFLAG_MSA 0x1000000
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#define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */
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target_ulong btarget; /* Jump / branch target */
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target_ulong bcond; /* Branch condition (if needed) */
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@ -843,7 +847,7 @@ static inline void compute_hflags(CPUMIPSState *env)
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env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
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MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
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MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
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MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA);
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MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE);
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if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
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!(env->CP0_Status & (1 << CP0St_ERL)) &&
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!(env->hflags & MIPS_HFLAG_DM)) {
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@ -924,6 +928,11 @@ static inline void compute_hflags(CPUMIPSState *env)
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env->hflags |= MIPS_HFLAG_MSA;
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}
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}
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if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
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if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
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env->hflags |= MIPS_HFLAG_FRE;
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}
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}
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}
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#ifndef CONFIG_USER_ONLY
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@ -2303,6 +2303,16 @@ target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
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}
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}
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break;
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case 5:
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/* FRE Support - read Config5.FRE bit */
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if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
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if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
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arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
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} else {
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helper_raise_exception(env, EXCP_RI);
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}
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}
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break;
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case 25:
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arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
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break;
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@ -2347,6 +2357,30 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
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helper_raise_exception(env, EXCP_RI);
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}
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break;
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case 5:
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/* FRE Support - clear Config5.FRE bit */
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if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
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return;
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}
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if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
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env->CP0_Config5 &= ~(1 << CP0C5_FRE);
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compute_hflags(env);
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} else {
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helper_raise_exception(env, EXCP_RI);
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}
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break;
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case 6:
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/* FRE Support - set Config5.FRE bit */
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if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
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return;
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}
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if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
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env->CP0_Config5 |= (1 << CP0C5_FRE);
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compute_hflags(env);
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} else {
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helper_raise_exception(env, EXCP_RI);
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}
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break;
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case 25:
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if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
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return;
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@ -1616,14 +1616,21 @@ static inline void generate_exception(DisasContext *ctx, int excp)
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}
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/* Floating point register moves. */
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static void gen_load_fpr32(TCGv_i32 t, int reg)
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static void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
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{
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if (ctx->hflags & MIPS_HFLAG_FRE) {
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generate_exception(ctx, EXCP_RI);
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}
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tcg_gen_trunc_i64_i32(t, fpu_f64[reg]);
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}
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static void gen_store_fpr32(TCGv_i32 t, int reg)
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static void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
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{
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TCGv_i64 t64 = tcg_temp_new_i64();
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TCGv_i64 t64;
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if (ctx->hflags & MIPS_HFLAG_FRE) {
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generate_exception(ctx, EXCP_RI);
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}
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t64 = tcg_temp_new_i64();
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tcg_gen_extu_i32_i64(t64, t);
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tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 0, 32);
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tcg_temp_free_i64(t64);
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@ -1637,7 +1644,7 @@ static void gen_load_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg)
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tcg_gen_trunc_i64_i32(t, t64);
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tcg_temp_free_i64(t64);
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} else {
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gen_load_fpr32(t, reg | 1);
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gen_load_fpr32(ctx, t, reg | 1);
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}
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}
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@ -1649,7 +1656,7 @@ static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg)
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tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 32, 32);
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tcg_temp_free_i64(t64);
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} else {
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gen_store_fpr32(t, reg | 1);
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gen_store_fpr32(ctx, t, reg | 1);
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}
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}
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@ -1817,7 +1824,7 @@ static inline void check_mips_64(DisasContext *ctx)
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calling interface for 32 and 64-bit FPRs. No sense in changing
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all callers for gen_load_fpr32 when we need the CTX parameter for
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this one use. */
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#define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(x, y)
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#define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(ctx, x, y)
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#define gen_ldcmp_fpr64(ctx, x, y) gen_load_fpr64(ctx, x, y)
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#define FOP_CONDS(type, abs, fmt, ifmt, bits) \
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static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
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@ -1961,7 +1968,7 @@ static inline void gen_r6_cmp_ ## fmt(DisasContext * ctx, int n, \
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}
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FOP_CONDNS(d, FMT_D, 64, gen_store_fpr64(ctx, fp0, fd))
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FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(fp0, fd))
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FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(ctx, fp0, fd))
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#undef FOP_CONDNS
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#undef gen_ldcmp_fpr32
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#undef gen_ldcmp_fpr64
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@ -2346,7 +2353,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
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{
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TCGv_i32 fp0 = tcg_temp_new_i32();
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tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL);
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gen_store_fpr32(fp0, ft);
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gen_store_fpr32(ctx, fp0, ft);
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tcg_temp_free_i32(fp0);
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}
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opn = "lwc1";
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@ -2354,7 +2361,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
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case OPC_SWC1:
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{
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TCGv_i32 fp0 = tcg_temp_new_i32();
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gen_load_fpr32(fp0, ft);
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gen_load_fpr32(ctx, fp0, ft);
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tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL);
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tcg_temp_free_i32(fp0);
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}
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@ -7555,7 +7562,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
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if (h == 0) {
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TCGv_i32 fp0 = tcg_temp_new_i32();
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gen_load_fpr32(fp0, rt);
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gen_load_fpr32(ctx, fp0, rt);
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tcg_gen_ext_i32_tl(t0, fp0);
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tcg_temp_free_i32(fp0);
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} else {
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@ -7754,7 +7761,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
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TCGv_i32 fp0 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(fp0, t0);
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gen_store_fpr32(fp0, rd);
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gen_store_fpr32(ctx, fp0, rd);
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tcg_temp_free_i32(fp0);
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} else {
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TCGv_i32 fp0 = tcg_temp_new_i32();
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@ -8344,7 +8351,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
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{
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TCGv_i32 fp0 = tcg_temp_new_i32();
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gen_load_fpr32(fp0, fs);
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gen_load_fpr32(ctx, fp0, fs);
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tcg_gen_ext_i32_tl(t0, fp0);
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tcg_temp_free_i32(fp0);
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}
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@ -8357,7 +8364,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
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TCGv_i32 fp0 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(fp0, t0);
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gen_store_fpr32(fp0, fs);
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gen_store_fpr32(ctx, fp0, fs);
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tcg_temp_free_i32(fp0);
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}
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opn = "mtc1";
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@ -8455,7 +8462,8 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
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gen_set_label(l1);
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}
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static inline void gen_movcf_s (int fs, int fd, int cc, int tf)
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static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc,
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int tf)
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{
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int cond;
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TCGv_i32 t0 = tcg_temp_new_i32();
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@ -8468,8 +8476,8 @@ static inline void gen_movcf_s (int fs, int fd, int cc, int tf)
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tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
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tcg_gen_brcondi_i32(cond, t0, 0, l1);
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gen_load_fpr32(t0, fs);
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gen_store_fpr32(t0, fd);
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gen_load_fpr32(ctx, t0, fs);
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gen_store_fpr32(ctx, t0, fd);
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gen_set_label(l1);
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tcg_temp_free_i32(t0);
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}
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@ -8511,8 +8519,8 @@ static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd,
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tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
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tcg_gen_brcondi_i32(cond, t0, 0, l1);
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gen_load_fpr32(t0, fs);
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gen_store_fpr32(t0, fd);
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gen_load_fpr32(ctx, t0, fs);
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gen_store_fpr32(ctx, t0, fd);
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gen_set_label(l1);
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tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc+1));
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@ -8530,9 +8538,9 @@ static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft,
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TCGv_i32 fp0 = tcg_temp_new_i32();
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TCGv_i32 fp1 = tcg_temp_new_i32();
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TCGv_i32 fp2 = tcg_temp_new_i32();
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gen_load_fpr32(fp0, fd);
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gen_load_fpr32(fp1, ft);
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gen_load_fpr32(fp2, fs);
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gen_load_fpr32(ctx, fp0, fd);
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gen_load_fpr32(ctx, fp1, ft);
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gen_load_fpr32(ctx, fp2, fs);
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switch (op1) {
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case OPC_SEL_S:
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@ -8553,7 +8561,7 @@ static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft,
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break;
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}
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gen_store_fpr32(fp0, fd);
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gen_store_fpr32(ctx, fp0, fd);
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tcg_temp_free_i32(fp2);
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tcg_temp_free_i32(fp1);
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tcg_temp_free_i32(fp0);
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@ -8646,11 +8654,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
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TCGv_i32 fp0 = tcg_temp_new_i32();
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TCGv_i32 fp1 = tcg_temp_new_i32();
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gen_load_fpr32(fp0, fs);
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gen_load_fpr32(fp1, ft);
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gen_load_fpr32(ctx, fp0, fs);
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gen_load_fpr32(ctx, fp1, ft);
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gen_helper_float_add_s(fp0, cpu_env, fp0, fp1);
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tcg_temp_free_i32(fp1);
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gen_store_fpr32(fp0, fd);
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gen_store_fpr32(ctx, fp0, fd);
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tcg_temp_free_i32(fp0);
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}
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opn = "add.s";
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@ -8661,11 +8669,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
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TCGv_i32 fp0 = tcg_temp_new_i32();
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TCGv_i32 fp1 = tcg_temp_new_i32();
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gen_load_fpr32(fp0, fs);
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gen_load_fpr32(fp1, ft);
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gen_load_fpr32(ctx, fp0, fs);
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gen_load_fpr32(ctx, fp1, ft);
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gen_helper_float_sub_s(fp0, cpu_env, fp0, fp1);
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tcg_temp_free_i32(fp1);
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gen_store_fpr32(fp0, fd);
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gen_store_fpr32(ctx, fp0, fd);
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tcg_temp_free_i32(fp0);
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}
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opn = "sub.s";
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@ -8676,11 +8684,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
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TCGv_i32 fp0 = tcg_temp_new_i32();
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TCGv_i32 fp1 = tcg_temp_new_i32();
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gen_load_fpr32(fp0, fs);
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gen_load_fpr32(fp1, ft);
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gen_load_fpr32(ctx, fp0, fs);
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gen_load_fpr32(ctx, fp1, ft);
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gen_helper_float_mul_s(fp0, cpu_env, fp0, fp1);
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tcg_temp_free_i32(fp1);
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gen_store_fpr32(fp0, fd);
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gen_store_fpr32(ctx, fp0, fd);
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tcg_temp_free_i32(fp0);
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}
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opn = "mul.s";
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@ -8691,11 +8699,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
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TCGv_i32 fp0 = tcg_temp_new_i32();
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TCGv_i32 fp1 = tcg_temp_new_i32();
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gen_load_fpr32(fp0, fs);
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gen_load_fpr32(fp1, ft);
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gen_load_fpr32(ctx, fp0, fs);
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gen_load_fpr32(ctx, fp1, ft);
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gen_helper_float_div_s(fp0, cpu_env, fp0, fp1);
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tcg_temp_free_i32(fp1);
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gen_store_fpr32(fp0, fd);
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gen_store_fpr32(ctx, fp0, fd);
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tcg_temp_free_i32(fp0);
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}
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opn = "div.s";
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@ -8705,9 +8713,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
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{
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TCGv_i32 fp0 = tcg_temp_new_i32();
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gen_load_fpr32(fp0, fs);
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gen_load_fpr32(ctx, fp0, fs);
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||||
gen_helper_float_sqrt_s(fp0, cpu_env, fp0);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
opn = "sqrt.s";
|
||||
|
|
@ -8716,9 +8724,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
{
|
||||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_abs_s(fp0, fp0);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
opn = "abs.s";
|
||||
|
|
@ -8727,8 +8735,8 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
{
|
||||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
opn = "mov.s";
|
||||
|
|
@ -8737,9 +8745,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
{
|
||||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_chs_s(fp0, fp0);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
opn = "neg.s";
|
||||
|
|
@ -8750,7 +8758,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp32 = tcg_temp_new_i32();
|
||||
TCGv_i64 fp64 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr32(fp32, fs);
|
||||
gen_load_fpr32(ctx, fp32, fs);
|
||||
gen_helper_float_roundl_s(fp64, cpu_env, fp32);
|
||||
tcg_temp_free_i32(fp32);
|
||||
gen_store_fpr64(ctx, fp64, fd);
|
||||
|
|
@ -8764,7 +8772,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp32 = tcg_temp_new_i32();
|
||||
TCGv_i64 fp64 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr32(fp32, fs);
|
||||
gen_load_fpr32(ctx, fp32, fs);
|
||||
gen_helper_float_truncl_s(fp64, cpu_env, fp32);
|
||||
tcg_temp_free_i32(fp32);
|
||||
gen_store_fpr64(ctx, fp64, fd);
|
||||
|
|
@ -8778,7 +8786,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp32 = tcg_temp_new_i32();
|
||||
TCGv_i64 fp64 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr32(fp32, fs);
|
||||
gen_load_fpr32(ctx, fp32, fs);
|
||||
gen_helper_float_ceill_s(fp64, cpu_env, fp32);
|
||||
tcg_temp_free_i32(fp32);
|
||||
gen_store_fpr64(ctx, fp64, fd);
|
||||
|
|
@ -8792,7 +8800,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp32 = tcg_temp_new_i32();
|
||||
TCGv_i64 fp64 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr32(fp32, fs);
|
||||
gen_load_fpr32(ctx, fp32, fs);
|
||||
gen_helper_float_floorl_s(fp64, cpu_env, fp32);
|
||||
tcg_temp_free_i32(fp32);
|
||||
gen_store_fpr64(ctx, fp64, fd);
|
||||
|
|
@ -8804,9 +8812,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
{
|
||||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_roundw_s(fp0, cpu_env, fp0);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
opn = "round.w.s";
|
||||
|
|
@ -8815,9 +8823,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
{
|
||||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_truncw_s(fp0, cpu_env, fp0);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
opn = "trunc.w.s";
|
||||
|
|
@ -8826,9 +8834,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
{
|
||||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_ceilw_s(fp0, cpu_env, fp0);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
opn = "ceil.w.s";
|
||||
|
|
@ -8837,9 +8845,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
{
|
||||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_floorw_s(fp0, cpu_env, fp0);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
opn = "floor.w.s";
|
||||
|
|
@ -8861,7 +8869,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
break;
|
||||
case OPC_MOVCF_S:
|
||||
check_insn_opc_removed(ctx, ISA_MIPS32R6);
|
||||
gen_movcf_s(fs, fd, (ft >> 2) & 0x7, ft & 0x1);
|
||||
gen_movcf_s(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
|
||||
opn = "movcf.s";
|
||||
break;
|
||||
case OPC_MOVZ_S:
|
||||
|
|
@ -8874,8 +8882,8 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
|
||||
}
|
||||
fp0 = tcg_temp_new_i32();
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
gen_set_label(l1);
|
||||
}
|
||||
|
|
@ -8890,8 +8898,8 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
if (ft != 0) {
|
||||
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
|
||||
fp0 = tcg_temp_new_i32();
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
gen_set_label(l1);
|
||||
}
|
||||
|
|
@ -8903,9 +8911,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
{
|
||||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_recip_s(fp0, cpu_env, fp0);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
opn = "recip.s";
|
||||
|
|
@ -8915,9 +8923,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
{
|
||||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_rsqrt_s(fp0, cpu_env, fp0);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
opn = "rsqrt.s";
|
||||
|
|
@ -8928,11 +8936,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
TCGv_i32 fp1 = tcg_temp_new_i32();
|
||||
TCGv_i32 fp2 = tcg_temp_new_i32();
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(fp1, ft);
|
||||
gen_load_fpr32(fp2, fd);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_load_fpr32(ctx, fp1, ft);
|
||||
gen_load_fpr32(ctx, fp2, fd);
|
||||
gen_helper_float_maddf_s(fp2, cpu_env, fp0, fp1, fp2);
|
||||
gen_store_fpr32(fp2, fd);
|
||||
gen_store_fpr32(ctx, fp2, fd);
|
||||
tcg_temp_free_i32(fp2);
|
||||
tcg_temp_free_i32(fp1);
|
||||
tcg_temp_free_i32(fp0);
|
||||
|
|
@ -8945,11 +8953,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
TCGv_i32 fp1 = tcg_temp_new_i32();
|
||||
TCGv_i32 fp2 = tcg_temp_new_i32();
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(fp1, ft);
|
||||
gen_load_fpr32(fp2, fd);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_load_fpr32(ctx, fp1, ft);
|
||||
gen_load_fpr32(ctx, fp2, fd);
|
||||
gen_helper_float_msubf_s(fp2, cpu_env, fp0, fp1, fp2);
|
||||
gen_store_fpr32(fp2, fd);
|
||||
gen_store_fpr32(ctx, fp2, fd);
|
||||
tcg_temp_free_i32(fp2);
|
||||
tcg_temp_free_i32(fp1);
|
||||
tcg_temp_free_i32(fp0);
|
||||
|
|
@ -8960,9 +8968,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
check_insn(ctx, ISA_MIPS32R6);
|
||||
{
|
||||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_rint_s(fp0, cpu_env, fp0);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
opn = "rint.s";
|
||||
}
|
||||
|
|
@ -8971,9 +8979,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
check_insn(ctx, ISA_MIPS32R6);
|
||||
{
|
||||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_class_s(fp0, fp0);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
opn = "class.s";
|
||||
}
|
||||
|
|
@ -8984,10 +8992,10 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
TCGv_i32 fp1 = tcg_temp_new_i32();
|
||||
TCGv_i32 fp2 = tcg_temp_new_i32();
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(fp1, ft);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_load_fpr32(ctx, fp1, ft);
|
||||
gen_helper_float_min_s(fp2, cpu_env, fp0, fp1);
|
||||
gen_store_fpr32(fp2, fd);
|
||||
gen_store_fpr32(ctx, fp2, fd);
|
||||
tcg_temp_free_i32(fp2);
|
||||
tcg_temp_free_i32(fp1);
|
||||
tcg_temp_free_i32(fp0);
|
||||
|
|
@ -8999,11 +9007,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
TCGv_i32 fp1 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(fp1, ft);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_load_fpr32(ctx, fp1, ft);
|
||||
gen_helper_float_recip2_s(fp0, cpu_env, fp0, fp1);
|
||||
tcg_temp_free_i32(fp1);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
opn = "recip2.s";
|
||||
|
|
@ -9015,10 +9023,10 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
TCGv_i32 fp1 = tcg_temp_new_i32();
|
||||
TCGv_i32 fp2 = tcg_temp_new_i32();
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(fp1, ft);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_load_fpr32(ctx, fp1, ft);
|
||||
gen_helper_float_mina_s(fp2, cpu_env, fp0, fp1);
|
||||
gen_store_fpr32(fp2, fd);
|
||||
gen_store_fpr32(ctx, fp2, fd);
|
||||
tcg_temp_free_i32(fp2);
|
||||
tcg_temp_free_i32(fp1);
|
||||
tcg_temp_free_i32(fp0);
|
||||
|
|
@ -9029,9 +9037,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
{
|
||||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_recip1_s(fp0, cpu_env, fp0);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
opn = "recip1.s";
|
||||
|
|
@ -9042,10 +9050,10 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
/* OPC_MAX_S */
|
||||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
TCGv_i32 fp1 = tcg_temp_new_i32();
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(fp1, ft);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_load_fpr32(ctx, fp1, ft);
|
||||
gen_helper_float_max_s(fp1, cpu_env, fp0, fp1);
|
||||
gen_store_fpr32(fp1, fd);
|
||||
gen_store_fpr32(ctx, fp1, fd);
|
||||
tcg_temp_free_i32(fp1);
|
||||
tcg_temp_free_i32(fp0);
|
||||
opn = "max.s";
|
||||
|
|
@ -9055,9 +9063,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
{
|
||||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_rsqrt1_s(fp0, cpu_env, fp0);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
opn = "rsqrt1.s";
|
||||
|
|
@ -9068,10 +9076,10 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
/* OPC_MAXA_S */
|
||||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
TCGv_i32 fp1 = tcg_temp_new_i32();
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(fp1, ft);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_load_fpr32(ctx, fp1, ft);
|
||||
gen_helper_float_maxa_s(fp1, cpu_env, fp0, fp1);
|
||||
gen_store_fpr32(fp1, fd);
|
||||
gen_store_fpr32(ctx, fp1, fd);
|
||||
tcg_temp_free_i32(fp1);
|
||||
tcg_temp_free_i32(fp0);
|
||||
opn = "maxa.s";
|
||||
|
|
@ -9082,11 +9090,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
TCGv_i32 fp1 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(fp1, ft);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_load_fpr32(ctx, fp1, ft);
|
||||
gen_helper_float_rsqrt2_s(fp0, cpu_env, fp0, fp1);
|
||||
tcg_temp_free_i32(fp1);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
opn = "rsqrt2.s";
|
||||
|
|
@ -9098,7 +9106,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp32 = tcg_temp_new_i32();
|
||||
TCGv_i64 fp64 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr32(fp32, fs);
|
||||
gen_load_fpr32(ctx, fp32, fs);
|
||||
gen_helper_float_cvtd_s(fp64, cpu_env, fp32);
|
||||
tcg_temp_free_i32(fp32);
|
||||
gen_store_fpr64(ctx, fp64, fd);
|
||||
|
|
@ -9110,9 +9118,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
{
|
||||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_cvtw_s(fp0, cpu_env, fp0);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
opn = "cvt.w.s";
|
||||
|
|
@ -9123,7 +9131,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp32 = tcg_temp_new_i32();
|
||||
TCGv_i64 fp64 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr32(fp32, fs);
|
||||
gen_load_fpr32(ctx, fp32, fs);
|
||||
gen_helper_float_cvtl_s(fp64, cpu_env, fp32);
|
||||
tcg_temp_free_i32(fp32);
|
||||
gen_store_fpr64(ctx, fp64, fd);
|
||||
|
|
@ -9139,8 +9147,8 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp32_0 = tcg_temp_new_i32();
|
||||
TCGv_i32 fp32_1 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp32_0, fs);
|
||||
gen_load_fpr32(fp32_1, ft);
|
||||
gen_load_fpr32(ctx, fp32_0, fs);
|
||||
gen_load_fpr32(ctx, fp32_1, ft);
|
||||
tcg_gen_concat_i32_i64(fp64, fp32_1, fp32_0);
|
||||
tcg_temp_free_i32(fp32_1);
|
||||
tcg_temp_free_i32(fp32_0);
|
||||
|
|
@ -9342,7 +9350,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
gen_load_fpr64(ctx, fp64, fs);
|
||||
gen_helper_float_roundw_d(fp32, cpu_env, fp64);
|
||||
tcg_temp_free_i64(fp64);
|
||||
gen_store_fpr32(fp32, fd);
|
||||
gen_store_fpr32(ctx, fp32, fd);
|
||||
tcg_temp_free_i32(fp32);
|
||||
}
|
||||
opn = "round.w.d";
|
||||
|
|
@ -9356,7 +9364,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
gen_load_fpr64(ctx, fp64, fs);
|
||||
gen_helper_float_truncw_d(fp32, cpu_env, fp64);
|
||||
tcg_temp_free_i64(fp64);
|
||||
gen_store_fpr32(fp32, fd);
|
||||
gen_store_fpr32(ctx, fp32, fd);
|
||||
tcg_temp_free_i32(fp32);
|
||||
}
|
||||
opn = "trunc.w.d";
|
||||
|
|
@ -9370,7 +9378,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
gen_load_fpr64(ctx, fp64, fs);
|
||||
gen_helper_float_ceilw_d(fp32, cpu_env, fp64);
|
||||
tcg_temp_free_i64(fp64);
|
||||
gen_store_fpr32(fp32, fd);
|
||||
gen_store_fpr32(ctx, fp32, fd);
|
||||
tcg_temp_free_i32(fp32);
|
||||
}
|
||||
opn = "ceil.w.d";
|
||||
|
|
@ -9384,7 +9392,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
gen_load_fpr64(ctx, fp64, fs);
|
||||
gen_helper_float_floorw_d(fp32, cpu_env, fp64);
|
||||
tcg_temp_free_i64(fp64);
|
||||
gen_store_fpr32(fp32, fd);
|
||||
gen_store_fpr32(ctx, fp32, fd);
|
||||
tcg_temp_free_i32(fp32);
|
||||
}
|
||||
opn = "floor.w.d";
|
||||
|
|
@ -9667,7 +9675,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
gen_load_fpr64(ctx, fp64, fs);
|
||||
gen_helper_float_cvts_d(fp32, cpu_env, fp64);
|
||||
tcg_temp_free_i64(fp64);
|
||||
gen_store_fpr32(fp32, fd);
|
||||
gen_store_fpr32(ctx, fp32, fd);
|
||||
tcg_temp_free_i32(fp32);
|
||||
}
|
||||
opn = "cvt.s.d";
|
||||
|
|
@ -9681,7 +9689,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
gen_load_fpr64(ctx, fp64, fs);
|
||||
gen_helper_float_cvtw_d(fp32, cpu_env, fp64);
|
||||
tcg_temp_free_i64(fp64);
|
||||
gen_store_fpr32(fp32, fd);
|
||||
gen_store_fpr32(ctx, fp32, fd);
|
||||
tcg_temp_free_i32(fp32);
|
||||
}
|
||||
opn = "cvt.w.d";
|
||||
|
|
@ -9702,9 +9710,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
{
|
||||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_cvts_w(fp0, cpu_env, fp0);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
opn = "cvt.s.w";
|
||||
|
|
@ -9715,7 +9723,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp32 = tcg_temp_new_i32();
|
||||
TCGv_i64 fp64 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr32(fp32, fs);
|
||||
gen_load_fpr32(ctx, fp32, fs);
|
||||
gen_helper_float_cvtd_w(fp64, cpu_env, fp32);
|
||||
tcg_temp_free_i32(fp32);
|
||||
gen_store_fpr64(ctx, fp64, fd);
|
||||
|
|
@ -9732,7 +9740,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
gen_load_fpr64(ctx, fp64, fs);
|
||||
gen_helper_float_cvts_l(fp32, cpu_env, fp64);
|
||||
tcg_temp_free_i64(fp64);
|
||||
gen_store_fpr32(fp32, fd);
|
||||
gen_store_fpr32(ctx, fp32, fd);
|
||||
tcg_temp_free_i32(fp32);
|
||||
}
|
||||
opn = "cvt.s.l";
|
||||
|
|
@ -9971,7 +9979,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
|
||||
gen_load_fpr32h(ctx, fp0, fs);
|
||||
gen_helper_float_cvts_pu(fp0, cpu_env, fp0);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
opn = "cvt.s.pu";
|
||||
|
|
@ -9993,9 +10001,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
{
|
||||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_cvts_pl(fp0, cpu_env, fp0);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
opn = "cvt.s.pl";
|
||||
|
|
@ -10006,10 +10014,10 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
TCGv_i32 fp1 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(fp1, ft);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_load_fpr32(ctx, fp1, ft);
|
||||
gen_store_fpr32h(ctx, fp0, fd);
|
||||
gen_store_fpr32(fp1, fd);
|
||||
gen_store_fpr32(ctx, fp1, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
tcg_temp_free_i32(fp1);
|
||||
}
|
||||
|
|
@ -10021,9 +10029,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
TCGv_i32 fp1 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_load_fpr32h(ctx, fp1, ft);
|
||||
gen_store_fpr32(fp1, fd);
|
||||
gen_store_fpr32(ctx, fp1, fd);
|
||||
gen_store_fpr32h(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
tcg_temp_free_i32(fp1);
|
||||
|
|
@ -10037,8 +10045,8 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp1 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32h(ctx, fp0, fs);
|
||||
gen_load_fpr32(fp1, ft);
|
||||
gen_store_fpr32(fp1, fd);
|
||||
gen_load_fpr32(ctx, fp1, ft);
|
||||
gen_store_fpr32(ctx, fp1, fd);
|
||||
gen_store_fpr32h(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
tcg_temp_free_i32(fp1);
|
||||
|
|
@ -10053,7 +10061,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
|
||||
gen_load_fpr32h(ctx, fp0, fs);
|
||||
gen_load_fpr32h(ctx, fp1, ft);
|
||||
gen_store_fpr32(fp1, fd);
|
||||
gen_store_fpr32(ctx, fp1, fd);
|
||||
gen_store_fpr32h(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
tcg_temp_free_i32(fp1);
|
||||
|
|
@ -10128,7 +10136,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
|
|||
|
||||
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
|
||||
tcg_gen_trunc_tl_i32(fp0, t0);
|
||||
gen_store_fpr32(fp0, fd);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
opn = "lwxc1";
|
||||
|
|
@ -10160,7 +10168,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
|
|||
check_cop1x(ctx);
|
||||
{
|
||||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
|
|
@ -10217,23 +10225,23 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
|
|||
tcg_gen_andi_tl(t0, t0, 0x7);
|
||||
|
||||
tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
|
||||
gen_load_fpr32(fp, fs);
|
||||
gen_load_fpr32(ctx, fp, fs);
|
||||
gen_load_fpr32h(ctx, fph, fs);
|
||||
gen_store_fpr32(fp, fd);
|
||||
gen_store_fpr32(ctx, fp, fd);
|
||||
gen_store_fpr32h(ctx, fph, fd);
|
||||
tcg_gen_br(l2);
|
||||
gen_set_label(l1);
|
||||
tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2);
|
||||
tcg_temp_free(t0);
|
||||
#ifdef TARGET_WORDS_BIGENDIAN
|
||||
gen_load_fpr32(fp, fs);
|
||||
gen_load_fpr32(ctx, fp, fs);
|
||||
gen_load_fpr32h(ctx, fph, ft);
|
||||
gen_store_fpr32h(ctx, fp, fd);
|
||||
gen_store_fpr32(fph, fd);
|
||||
gen_store_fpr32(ctx, fph, fd);
|
||||
#else
|
||||
gen_load_fpr32h(ctx, fph, fs);
|
||||
gen_load_fpr32(fp, ft);
|
||||
gen_store_fpr32(fph, fd);
|
||||
gen_load_fpr32(ctx, fp, ft);
|
||||
gen_store_fpr32(ctx, fph, fd);
|
||||
gen_store_fpr32h(ctx, fp, fd);
|
||||
#endif
|
||||
gen_set_label(l2);
|
||||
|
|
@ -10249,13 +10257,13 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
|
|||
TCGv_i32 fp1 = tcg_temp_new_i32();
|
||||
TCGv_i32 fp2 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(fp1, ft);
|
||||
gen_load_fpr32(fp2, fr);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_load_fpr32(ctx, fp1, ft);
|
||||
gen_load_fpr32(ctx, fp2, fr);
|
||||
gen_helper_float_madd_s(fp2, cpu_env, fp0, fp1, fp2);
|
||||
tcg_temp_free_i32(fp0);
|
||||
tcg_temp_free_i32(fp1);
|
||||
gen_store_fpr32(fp2, fd);
|
||||
gen_store_fpr32(ctx, fp2, fd);
|
||||
tcg_temp_free_i32(fp2);
|
||||
}
|
||||
opn = "madd.s";
|
||||
|
|
@ -10304,13 +10312,13 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
|
|||
TCGv_i32 fp1 = tcg_temp_new_i32();
|
||||
TCGv_i32 fp2 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(fp1, ft);
|
||||
gen_load_fpr32(fp2, fr);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_load_fpr32(ctx, fp1, ft);
|
||||
gen_load_fpr32(ctx, fp2, fr);
|
||||
gen_helper_float_msub_s(fp2, cpu_env, fp0, fp1, fp2);
|
||||
tcg_temp_free_i32(fp0);
|
||||
tcg_temp_free_i32(fp1);
|
||||
gen_store_fpr32(fp2, fd);
|
||||
gen_store_fpr32(ctx, fp2, fd);
|
||||
tcg_temp_free_i32(fp2);
|
||||
}
|
||||
opn = "msub.s";
|
||||
|
|
@ -10359,13 +10367,13 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
|
|||
TCGv_i32 fp1 = tcg_temp_new_i32();
|
||||
TCGv_i32 fp2 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(fp1, ft);
|
||||
gen_load_fpr32(fp2, fr);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_load_fpr32(ctx, fp1, ft);
|
||||
gen_load_fpr32(ctx, fp2, fr);
|
||||
gen_helper_float_nmadd_s(fp2, cpu_env, fp0, fp1, fp2);
|
||||
tcg_temp_free_i32(fp0);
|
||||
tcg_temp_free_i32(fp1);
|
||||
gen_store_fpr32(fp2, fd);
|
||||
gen_store_fpr32(ctx, fp2, fd);
|
||||
tcg_temp_free_i32(fp2);
|
||||
}
|
||||
opn = "nmadd.s";
|
||||
|
|
@ -10414,13 +10422,13 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
|
|||
TCGv_i32 fp1 = tcg_temp_new_i32();
|
||||
TCGv_i32 fp2 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(fp0, fs);
|
||||
gen_load_fpr32(fp1, ft);
|
||||
gen_load_fpr32(fp2, fr);
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_load_fpr32(ctx, fp1, ft);
|
||||
gen_load_fpr32(ctx, fp2, fr);
|
||||
gen_helper_float_nmsub_s(fp2, cpu_env, fp0, fp1, fp2);
|
||||
tcg_temp_free_i32(fp0);
|
||||
tcg_temp_free_i32(fp1);
|
||||
gen_store_fpr32(fp2, fd);
|
||||
gen_store_fpr32(ctx, fp2, fd);
|
||||
tcg_temp_free_i32(fp2);
|
||||
}
|
||||
opn = "nmsub.s";
|
||||
|
|
@ -13500,7 +13508,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx,
|
|||
case MOVF_FMT:
|
||||
switch (fmt) {
|
||||
case FMT_SDPS_S:
|
||||
gen_movcf_s(rs, rt, cc, 0);
|
||||
gen_movcf_s(ctx, rs, rt, cc, 0);
|
||||
break;
|
||||
case FMT_SDPS_D:
|
||||
gen_movcf_d(ctx, rs, rt, cc, 0);
|
||||
|
|
@ -13515,7 +13523,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx,
|
|||
case MOVT_FMT:
|
||||
switch (fmt) {
|
||||
case FMT_SDPS_S:
|
||||
gen_movcf_s(rs, rt, cc, 1);
|
||||
gen_movcf_s(ctx, rs, rt, cc, 1);
|
||||
break;
|
||||
case FMT_SDPS_D:
|
||||
gen_movcf_d(ctx, rs, rt, cc, 1);
|
||||
|
|
|
|||
|
|
@ -622,7 +622,8 @@ static const mips_def_t mips_defs[] =
|
|||
(1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1U << CP0C3_M),
|
||||
.CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
|
||||
(3 << CP0C4_IE) | (1 << CP0C4_M),
|
||||
.CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI),
|
||||
.CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
|
||||
(1 << CP0C5_UFE),
|
||||
.CP0_LLAddr_rw_bitmask = 0,
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||||
.CP0_LLAddr_shift = 0,
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.SYNCI_Step = 32,
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|
@ -631,9 +632,9 @@ static const mips_def_t mips_defs[] =
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.CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
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(1U << CP0PG_RIE),
|
||||
.CP0_PageGrain_rw_bitmask = 0,
|
||||
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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(1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) |
|
||||
(0x0 << FCR0_REV),
|
||||
.CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_F64) | (1 << FCR0_L) |
|
||||
(1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
|
||||
(0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
|
||||
.SEGBITS = 42,
|
||||
/* The architectural limit is 59, but we have hardcoded 36 bit
|
||||
in some places...
|
||||
|
|
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Loading…
Reference in a new issue