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https://gitlab.com/qemu-project/qemu
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target/hexagon: prepare input for the idef-parser
Introduce infrastructure necessary to produce a file suitable for being parsed by the idef-parser. A build option is also added to fully disable the output of idef-parser, which is useful for debugging. Signed-off-by: Alessandro Di Federico <ale@rev.ng> Signed-off-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220923173831.227551-8-anjo@rev.ng>
This commit is contained in:
Alessandro Di Federico
Taylor Simpson
parent
42659e046f
commit
7c19dcc564
5 changed files with 317 additions and 0 deletions
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@ -321,3 +321,6 @@ option('profiler', type: 'boolean', value: false,
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description: 'profiler support')
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option('slirp_smbd', type : 'feature', value : 'auto',
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description: 'use smbd (at path --smbd=*) in slirp networking')
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option('hexagon_idef_parser', type : 'boolean', value : true,
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description: 'use idef-parser to automatically generate TCG code for the Hexagon frontend')
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130
target/hexagon/gen_idef_parser_funcs.py
Normal file
130
target/hexagon/gen_idef_parser_funcs.py
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@ -0,0 +1,130 @@
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#!/usr/bin/env python3
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##
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## Copyright(c) 2019-2022 rev.ng Labs Srl. All Rights Reserved.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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import sys
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import re
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import string
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from io import StringIO
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import hex_common
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##
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## Generate code to be fed to the idef_parser
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##
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## Consider A2_add:
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##
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## Rd32=add(Rs32,Rt32), { RdV=RsV+RtV;}
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##
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## We produce:
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##
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## A2_add(RdV, in RsV, in RtV) {
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## { RdV=RsV+RtV;}
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## }
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##
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## A2_add represents the instruction tag. Then we have a list of TCGv
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## that the code generated by the parser can expect in input. Some of
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## them are inputs ("in" prefix), while some others are outputs.
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##
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def main():
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hex_common.read_semantics_file(sys.argv[1])
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hex_common.read_attribs_file(sys.argv[2])
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hex_common.calculate_attribs()
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tagregs = hex_common.get_tagregs()
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tagimms = hex_common.get_tagimms()
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with open(sys.argv[3], 'w') as f:
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f.write('#include "macros.inc"\n\n')
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for tag in hex_common.tags:
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## Skip the priv instructions
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if ( "A_PRIV" in hex_common.attribdict[tag] ) :
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continue
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## Skip the guest instructions
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if ( "A_GUEST" in hex_common.attribdict[tag] ) :
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continue
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## Skip instructions that saturate in a ternary expression
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if ( tag in {'S2_asr_r_r_sat', 'S2_asl_r_r_sat'} ) :
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continue
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## Skip instructions using switch
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if ( tag in {'S4_vrcrotate_acc', 'S4_vrcrotate'} ) :
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continue
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## Skip trap instructions
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if ( tag in {'J2_trap0', 'J2_trap1'} ) :
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continue
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## Skip 128-bit instructions
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if ( tag in {'A7_croundd_ri', 'A7_croundd_rr'} ) :
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continue
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if ( tag in {'M7_wcmpyrw', 'M7_wcmpyrwc',
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'M7_wcmpyiw', 'M7_wcmpyiwc',
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'M7_wcmpyrw_rnd', 'M7_wcmpyrwc_rnd',
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'M7_wcmpyiw_rnd', 'M7_wcmpyiwc_rnd'} ) :
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continue
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## Skip interleave/deinterleave instructions
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if ( tag in {'S2_interleave', 'S2_deinterleave'} ) :
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continue
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## Skip instructions using bit reverse
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if ( tag in {'S2_brev', 'S2_brevp', 'S2_ct0', 'S2_ct1',
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'S2_ct0p', 'S2_ct1p', 'A4_tlbmatch'} ) :
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continue
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## Skip other unsupported instructions
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if ( tag == 'S2_cabacdecbin' or tag == 'A5_ACS' ) :
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continue
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if ( tag.startswith('Y') ) :
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continue
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if ( tag.startswith('V6_') ) :
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continue
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if ( tag.startswith('F') ) :
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continue
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if ( tag.endswith('_locked') ) :
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continue
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if ( "A_COF" in hex_common.attribdict[tag] ) :
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continue
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regs = tagregs[tag]
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imms = tagimms[tag]
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arguments = []
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for regtype,regid,toss,numregs in regs:
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prefix = "in " if hex_common.is_read(regid) else ""
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is_pair = hex_common.is_pair(regid)
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is_single_old = (hex_common.is_single(regid)
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and hex_common.is_old_val(regtype, regid, tag))
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is_single_new = (hex_common.is_single(regid)
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and hex_common.is_new_val(regtype, regid, tag))
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if is_pair or is_single_old:
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arguments.append("%s%s%sV" % (prefix, regtype, regid))
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elif is_single_new:
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arguments.append("%s%s%sN" % (prefix, regtype, regid))
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else:
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print("Bad register parse: ",regtype,regid,toss,numregs)
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for immlett,bits,immshift in imms:
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arguments.append(hex_common.imm_name(immlett))
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f.write("%s(%s) {\n" % (tag, ", ".join(arguments)))
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f.write(" ");
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if hex_common.need_ea(tag):
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f.write("size4u_t EA; ");
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f.write("%s\n" % hex_common.semdict[tag])
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f.write("}\n\n")
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if __name__ == "__main__":
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main()
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140
target/hexagon/idef-parser/macros.inc
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140
target/hexagon/idef-parser/macros.inc
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@ -0,0 +1,140 @@
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/*
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* Copyright(c) 2019-2022 rev.ng Labs Srl. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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/* Copy rules */
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#define fLSBOLD(VAL) (fGETBIT(0, VAL))
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#define fSATH(VAL) fSATN(16, VAL)
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#define fSATUH(VAL) fSATUN(16, VAL)
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#define fVSATH(VAL) fVSATN(16, VAL)
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#define fVSATUH(VAL) fVSATUN(16, VAL)
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#define fSATUB(VAL) fSATUN(8, VAL)
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#define fSATB(VAL) fSATN(8, VAL)
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#define fVSATUB(VAL) fVSATUN(8, VAL)
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#define fVSATB(VAL) fVSATN(8, VAL)
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#define fCALL(A) fWRITE_LR(fREAD_NPC()); fWRITE_NPC(A);
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#define fCALLR(A) fWRITE_LR(fREAD_NPC()); fWRITE_NPC(A);
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#define fCAST2_8s(A) fSXTN(16, 64, A)
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#define fCAST2_8u(A) fZXTN(16, 64, A)
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#define fVSATW(A) fVSATN(32, fCAST8_8s(A))
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#define fSATW(A) fSATN(32, fCAST8_8s(A))
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#define fVSAT(A) fVSATN(32, A)
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#define fSAT(A) fSATN(32, A)
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/* Ease parsing */
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#define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00)
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#define fREAD_GP() (Constant_extended ? (0) : GP)
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#define fCLIP(DST, SRC, U) (DST = fMIN((1 << U) - 1, fMAX(SRC, -(1 << U))))
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#define fBIDIR_ASHIFTL(SRC, SHAMT, REGSTYPE) \
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((SHAMT > 0) ? \
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(fCAST##REGSTYPE##s(SRC) << SHAMT) : \
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(fCAST##REGSTYPE##s(SRC) >> -SHAMT))
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#define fBIDIR_LSHIFTL(SRC, SHAMT, REGSTYPE) \
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((SHAMT > 0) ? \
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(fCAST##REGSTYPE##u(SRC) << SHAMT) : \
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(fCAST##REGSTYPE##u(SRC) >>> -SHAMT))
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#define fBIDIR_ASHIFTR(SRC, SHAMT, REGSTYPE) \
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((SHAMT > 0) ? \
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(fCAST##REGSTYPE##s(SRC) >> SHAMT) : \
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(fCAST##REGSTYPE##s(SRC) << -SHAMT))
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#define fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE) \
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(((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT)) - 1)) << 1) \
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: (fCAST##REGSTYPE(SRC) >> (SHAMT)))
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#define fBIDIR_LSHIFTR(SRC, SHAMT, REGSTYPE) \
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fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##u)
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#define fSATVALN(N, VAL) \
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fSET_OVERFLOW( \
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((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1) \
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)
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#define fSAT_ORIG_SHL(A, ORIG_REG) \
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(((fCAST4s((fSAT(A)) ^ (fCAST4s(ORIG_REG)))) < 0) \
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? fSATVALN(32, (fCAST4s(ORIG_REG))) \
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: ((((ORIG_REG) > 0) && ((A) == 0)) ? fSATVALN(32, (ORIG_REG)) \
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: fSAT(A)))
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#define fBIDIR_ASHIFTR_SAT(SRC, SHAMT, REGSTYPE) \
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(((SHAMT) < 0) ? fSAT_ORIG_SHL((fCAST##REGSTYPE##s(SRC) \
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<< ((-(SHAMT)) - 1)) << 1, (SRC)) \
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: (fCAST##REGSTYPE##s(SRC) >> (SHAMT)))
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#define fBIDIR_ASHIFTL_SAT(SRC, SHAMT, REGSTYPE) \
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(((SHAMT) < 0) \
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? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT)) - 1)) >> 1) \
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: fSAT_ORIG_SHL(fCAST##REGSTYPE##s(SRC) << (SHAMT), (SRC)))
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#define fEXTRACTU_BIDIR(INREG, WIDTH, OFFSET) \
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(fZXTN(WIDTH, 32, fBIDIR_LSHIFTR((INREG), (OFFSET), 4_8)))
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/* Least significant bit operations */
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#define fLSBNEW0 fLSBNEW(P0N)
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#define fLSBNEW1 fLSBNEW(P1N)
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#define fLSBOLDNOT(VAL) fGETBIT(0, ~VAL)
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#define fLSBNEWNOT(PRED) (fLSBNEW(~PRED))
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#define fLSBNEW0NOT fLSBNEW(~P0N)
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#define fLSBNEW1NOT fLSBNEW(~P1N)
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/* Assignments */
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#define fPCALIGN(IMM) (IMM = IMM & ~3)
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#define fWRITE_LR(A) (LR = A)
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#define fWRITE_FP(A) (FP = A)
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#define fWRITE_SP(A) (SP = A)
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/*
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* Note: There is a rule in the parser that matches `PC = ...` and emits
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* a call to `gen_write_new_pc`. We need to call `gen_write_new_pc` to
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* get the correct semantics when there are multiple stores in a packet.
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*/
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#define fBRANCH(LOC, TYPE) (PC = LOC)
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#define fJUMPR(REGNO, TARGET, TYPE) (PC = TARGET)
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#define fWRITE_LOOP_REGS0(START, COUNT) SA0 = START; (LC0 = COUNT)
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#define fWRITE_LOOP_REGS1(START, COUNT) SA1 = START; (LC1 = COUNT)
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#define fWRITE_LC0(VAL) (LC0 = VAL)
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#define fWRITE_LC1(VAL) (LC1 = VAL)
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#define fSET_LPCFG(VAL) (USR.LPCFG = VAL)
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#define fWRITE_P0(VAL) P0 = VAL;
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#define fWRITE_P1(VAL) P1 = VAL;
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#define fWRITE_P3(VAL) P3 = VAL;
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#define fEA_RI(REG, IMM) (EA = REG + IMM)
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#define fEA_RRs(REG, REG2, SCALE) (EA = REG + (REG2 << SCALE))
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#define fEA_IRs(IMM, REG, SCALE) (EA = IMM + (REG << SCALE))
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#define fEA_IMM(IMM) (EA = IMM)
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#define fEA_REG(REG) (EA = REG)
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#define fEA_BREVR(REG) (EA = fbrev(REG))
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#define fEA_GPI(IMM) (EA = fREAD_GP() + IMM)
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#define fPM_I(REG, IMM) (REG = REG + IMM)
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#define fPM_M(REG, MVAL) (REG = REG + MVAL)
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#define fWRITE_NPC(VAL) (PC = VAL)
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/* Unary operators */
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#define fROUND(A) (A + 0x8000)
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/* Binary operators */
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#define fSCALE(N, A) (A << N)
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#define fASHIFTR(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) >> SHAMT)
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#define fLSHIFTR(SRC, SHAMT, REGSTYPE) (SRC >>> SHAMT)
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#define fROTL(SRC, SHAMT, REGSTYPE) fROTL(SRC, SHAMT)
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#define fASHIFTL(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) << SHAMT)
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/* Include fHIDE macros which hide type declarations */
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#define fHIDE(A) A
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/* Purge non-relavant parts */
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#define fBRANCH_SPECULATE_STALL(A, B, C, D, E)
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24
target/hexagon/idef-parser/prepare
Executable file
24
target/hexagon/idef-parser/prepare
Executable file
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@ -0,0 +1,24 @@
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#!/bin/bash
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#
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# Copyright(c) 2019-2021 rev.ng Labs Srl. All Rights Reserved.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, see <http://www.gnu.org/licenses/>.
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#
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set -e
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set -o pipefail
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# Run the preprocessor and drop comments
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cpp "$@"
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@ -21,6 +21,7 @@ hex_common_py = 'hex_common.py'
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attribs_def = meson.current_source_dir() / 'attribs_def.h.inc'
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gen_tcg_h = meson.current_source_dir() / 'gen_tcg.h'
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gen_tcg_hvx_h = meson.current_source_dir() / 'gen_tcg_hvx.h'
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idef_parser_dir = meson.current_source_dir() / 'idef-parser'
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#
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# Step 1
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@ -179,4 +180,23 @@ hexagon_ss.add(files(
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'mmvec/system_ext_mmvec.c',
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))
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idef_parser_enabled = get_option('hexagon_idef_parser')
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if idef_parser_enabled and 'hexagon-linux-user' in target_dirs
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idef_parser_input_generated = custom_target(
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'idef_parser_input.h.inc',
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output: 'idef_parser_input.h.inc',
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depends: [semantics_generated],
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depend_files: [hex_common_py],
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command: [python, files('gen_idef_parser_funcs.py'), semantics_generated, attribs_def, '@OUTPUT@'],
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)
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preprocessed_idef_parser_input_generated = custom_target(
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'idef_parser_input.preprocessed.h.inc',
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output: 'idef_parser_input.preprocessed.h.inc',
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input: idef_parser_input_generated,
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depend_files: [idef_parser_dir / 'macros.inc'],
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command: [idef_parser_dir / 'prepare', '@INPUT@', '-I' + idef_parser_dir, '-o', '@OUTPUT@'],
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)
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endif
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target_arch += {'hexagon': hexagon_ss}
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