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https://gitlab.com/qemu-project/qemu
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pcie: Add support for Single Root I/O Virtualization (SR/IOV)
This patch provides the building blocks for creating an SR/IOV PCIe Extended Capability header and register/unregister SR/IOV Virtual Functions. Signed-off-by: Knut Omang <knuto@ifi.uio.no> Message-Id: <20220217174504.1051716-2-lukasz.maniak@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
parent
0ea5778f06
commit
7c0fa8dff8
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@ -5,6 +5,7 @@ pci_ss.add(files(
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'pci.c',
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'pci_bridge.c',
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'pci_host.c',
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'pcie_sriov.c',
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'shpc.c',
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'slotid_cap.c'
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))
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100
hw/pci/pci.c
100
hw/pci/pci.c
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@ -239,6 +239,9 @@ int pci_bar(PCIDevice *d, int reg)
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{
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uint8_t type;
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/* PCIe virtual functions do not have their own BARs */
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assert(!pci_is_vf(d));
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if (reg != PCI_ROM_SLOT)
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return PCI_BASE_ADDRESS_0 + reg * 4;
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@ -304,10 +307,30 @@ void pci_device_deassert_intx(PCIDevice *dev)
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}
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}
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static void pci_do_device_reset(PCIDevice *dev)
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static void pci_reset_regions(PCIDevice *dev)
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{
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int r;
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if (pci_is_vf(dev)) {
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return;
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}
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for (r = 0; r < PCI_NUM_REGIONS; ++r) {
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PCIIORegion *region = &dev->io_regions[r];
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if (!region->size) {
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continue;
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}
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if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
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region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
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pci_set_quad(dev->config + pci_bar(dev, r), region->type);
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} else {
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pci_set_long(dev->config + pci_bar(dev, r), region->type);
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}
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}
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}
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static void pci_do_device_reset(PCIDevice *dev)
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{
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pci_device_deassert_intx(dev);
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assert(dev->irq_state == 0);
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@ -323,19 +346,7 @@ static void pci_do_device_reset(PCIDevice *dev)
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pci_get_word(dev->wmask + PCI_INTERRUPT_LINE) |
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pci_get_word(dev->w1cmask + PCI_INTERRUPT_LINE));
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dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
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for (r = 0; r < PCI_NUM_REGIONS; ++r) {
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PCIIORegion *region = &dev->io_regions[r];
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if (!region->size) {
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continue;
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}
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if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
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region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
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pci_set_quad(dev->config + pci_bar(dev, r), region->type);
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} else {
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pci_set_long(dev->config + pci_bar(dev, r), region->type);
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}
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}
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pci_reset_regions(dev);
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pci_update_mappings(dev);
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msi_reset(dev);
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@ -884,6 +895,16 @@ static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp)
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dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
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}
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/*
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* With SR/IOV and ARI, a device at function 0 need not be a multifunction
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* device, as it may just be a VF that ended up with function 0 in
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* the legacy PCI interpretation. Avoid failing in such cases:
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*/
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if (pci_is_vf(dev) &&
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dev->exp.sriov_vf.pf->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
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return;
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}
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/*
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* multifunction bit is interpreted in two ways as follows.
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* - all functions must set the bit to 1.
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@ -1083,6 +1104,7 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev,
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bus->devices[devfn]->name);
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return NULL;
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} else if (dev->hotplugged &&
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!pci_is_vf(pci_dev) &&
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pci_get_function_0(pci_dev)) {
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error_setg(errp, "PCI: slot %d function 0 already occupied by %s,"
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" new func %s cannot be exposed to guest.",
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@ -1191,6 +1213,7 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num,
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pcibus_t size = memory_region_size(memory);
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uint8_t hdr_type;
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assert(!pci_is_vf(pci_dev)); /* VFs must use pcie_sriov_vf_register_bar */
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assert(region_num >= 0);
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assert(region_num < PCI_NUM_REGIONS);
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assert(is_power_of_2(size));
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@ -1294,11 +1317,45 @@ pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
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return pci_dev->io_regions[region_num].addr;
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}
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static pcibus_t pci_bar_address(PCIDevice *d,
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int reg, uint8_t type, pcibus_t size)
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static pcibus_t pci_config_get_bar_addr(PCIDevice *d, int reg,
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uint8_t type, pcibus_t size)
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{
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pcibus_t new_addr;
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if (!pci_is_vf(d)) {
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int bar = pci_bar(d, reg);
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if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
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new_addr = pci_get_quad(d->config + bar);
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} else {
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new_addr = pci_get_long(d->config + bar);
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}
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} else {
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PCIDevice *pf = d->exp.sriov_vf.pf;
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uint16_t sriov_cap = pf->exp.sriov_cap;
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int bar = sriov_cap + PCI_SRIOV_BAR + reg * 4;
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uint16_t vf_offset =
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pci_get_word(pf->config + sriov_cap + PCI_SRIOV_VF_OFFSET);
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uint16_t vf_stride =
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pci_get_word(pf->config + sriov_cap + PCI_SRIOV_VF_STRIDE);
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uint32_t vf_num = (d->devfn - (pf->devfn + vf_offset)) / vf_stride;
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if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
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new_addr = pci_get_quad(pf->config + bar);
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} else {
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new_addr = pci_get_long(pf->config + bar);
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}
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new_addr += vf_num * size;
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}
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/* The ROM slot has a specific enable bit, keep it intact */
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if (reg != PCI_ROM_SLOT) {
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new_addr &= ~(size - 1);
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}
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return new_addr;
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}
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pcibus_t pci_bar_address(PCIDevice *d,
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int reg, uint8_t type, pcibus_t size)
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{
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pcibus_t new_addr, last_addr;
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int bar = pci_bar(d, reg);
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uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
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Object *machine = qdev_get_machine();
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ObjectClass *oc = object_get_class(machine);
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@ -1309,7 +1366,7 @@ static pcibus_t pci_bar_address(PCIDevice *d,
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if (!(cmd & PCI_COMMAND_IO)) {
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return PCI_BAR_UNMAPPED;
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}
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new_addr = pci_get_long(d->config + bar) & ~(size - 1);
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new_addr = pci_config_get_bar_addr(d, reg, type, size);
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last_addr = new_addr + size - 1;
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/* Check if 32 bit BAR wraps around explicitly.
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* TODO: make priorities correct and remove this work around.
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@ -1324,11 +1381,7 @@ static pcibus_t pci_bar_address(PCIDevice *d,
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if (!(cmd & PCI_COMMAND_MEMORY)) {
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return PCI_BAR_UNMAPPED;
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}
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if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
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new_addr = pci_get_quad(d->config + bar);
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} else {
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new_addr = pci_get_long(d->config + bar);
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}
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new_addr = pci_config_get_bar_addr(d, reg, type, size);
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/* the ROM slot has a specific enable bit */
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if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
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return PCI_BAR_UNMAPPED;
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@ -1473,6 +1526,7 @@ void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int
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msi_write_config(d, addr, val_in, l);
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msix_write_config(d, addr, val_in, l);
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pcie_sriov_config_write(d, addr, val_in, l);
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}
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/***********************************************************/
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@ -446,6 +446,11 @@ void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
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PCIDevice *pci_dev = PCI_DEVICE(dev);
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uint32_t lnkcap = pci_get_long(exp_cap + PCI_EXP_LNKCAP);
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if (pci_is_vf(pci_dev)) {
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/* Virtual function cannot be physically disconnected */
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return;
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}
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/* Don't send event when device is enabled during qemu machine creation:
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* it is present on boot, no hotplug event is necessary. We do send an
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* event when the device is disabled later. */
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294
hw/pci/pcie_sriov.c
Normal file
294
hw/pci/pcie_sriov.c
Normal file
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/*
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* pcie_sriov.c:
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*
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* Implementation of SR/IOV emulation support.
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*
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* Copyright (c) 2015-2017 Knut Omang <knut.omang@oracle.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include "qemu/osdep.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pcie.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/qdev-properties.h"
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#include "qemu/error-report.h"
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#include "qemu/range.h"
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#include "qapi/error.h"
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#include "trace.h"
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static PCIDevice *register_vf(PCIDevice *pf, int devfn,
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const char *name, uint16_t vf_num);
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static void unregister_vfs(PCIDevice *dev);
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void pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset,
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const char *vfname, uint16_t vf_dev_id,
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uint16_t init_vfs, uint16_t total_vfs,
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uint16_t vf_offset, uint16_t vf_stride)
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{
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uint8_t *cfg = dev->config + offset;
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uint8_t *wmask;
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pcie_add_capability(dev, PCI_EXT_CAP_ID_SRIOV, 1,
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offset, PCI_EXT_CAP_SRIOV_SIZEOF);
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dev->exp.sriov_cap = offset;
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dev->exp.sriov_pf.num_vfs = 0;
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dev->exp.sriov_pf.vfname = g_strdup(vfname);
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dev->exp.sriov_pf.vf = NULL;
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pci_set_word(cfg + PCI_SRIOV_VF_OFFSET, vf_offset);
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pci_set_word(cfg + PCI_SRIOV_VF_STRIDE, vf_stride);
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/*
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* Mandatory page sizes to support.
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* Device implementations can call pcie_sriov_pf_add_sup_pgsize()
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* to set more bits:
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*/
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pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, SRIOV_SUP_PGSIZE_MINREQ);
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/*
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* Default is to use 4K pages, software can modify it
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* to any of the supported bits
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*/
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pci_set_word(cfg + PCI_SRIOV_SYS_PGSIZE, 0x1);
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/* Set up device ID and initial/total number of VFs available */
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pci_set_word(cfg + PCI_SRIOV_VF_DID, vf_dev_id);
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pci_set_word(cfg + PCI_SRIOV_INITIAL_VF, init_vfs);
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pci_set_word(cfg + PCI_SRIOV_TOTAL_VF, total_vfs);
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pci_set_word(cfg + PCI_SRIOV_NUM_VF, 0);
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/* Write enable control bits */
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wmask = dev->wmask + offset;
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pci_set_word(wmask + PCI_SRIOV_CTRL,
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PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI);
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pci_set_word(wmask + PCI_SRIOV_NUM_VF, 0xffff);
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pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, 0x553);
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qdev_prop_set_bit(&dev->qdev, "multifunction", true);
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}
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void pcie_sriov_pf_exit(PCIDevice *dev)
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{
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unregister_vfs(dev);
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g_free((char *)dev->exp.sriov_pf.vfname);
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dev->exp.sriov_pf.vfname = NULL;
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}
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void pcie_sriov_pf_init_vf_bar(PCIDevice *dev, int region_num,
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uint8_t type, dma_addr_t size)
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{
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uint32_t addr;
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uint64_t wmask;
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uint16_t sriov_cap = dev->exp.sriov_cap;
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assert(sriov_cap > 0);
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assert(region_num >= 0);
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assert(region_num < PCI_NUM_REGIONS);
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assert(region_num != PCI_ROM_SLOT);
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wmask = ~(size - 1);
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addr = sriov_cap + PCI_SRIOV_BAR + region_num * 4;
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pci_set_long(dev->config + addr, type);
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if (!(type & PCI_BASE_ADDRESS_SPACE_IO) &&
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type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
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pci_set_quad(dev->wmask + addr, wmask);
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pci_set_quad(dev->cmask + addr, ~0ULL);
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} else {
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pci_set_long(dev->wmask + addr, wmask & 0xffffffff);
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pci_set_long(dev->cmask + addr, 0xffffffff);
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}
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dev->exp.sriov_pf.vf_bar_type[region_num] = type;
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}
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void pcie_sriov_vf_register_bar(PCIDevice *dev, int region_num,
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MemoryRegion *memory)
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{
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PCIIORegion *r;
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PCIBus *bus = pci_get_bus(dev);
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uint8_t type;
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pcibus_t size = memory_region_size(memory);
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assert(pci_is_vf(dev)); /* PFs must use pci_register_bar */
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assert(region_num >= 0);
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assert(region_num < PCI_NUM_REGIONS);
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type = dev->exp.sriov_vf.pf->exp.sriov_pf.vf_bar_type[region_num];
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if (!is_power_of_2(size)) {
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error_report("%s: PCI region size must be a power"
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" of two - type=0x%x, size=0x%"FMT_PCIBUS,
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__func__, type, size);
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exit(1);
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}
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r = &dev->io_regions[region_num];
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r->memory = memory;
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r->address_space =
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type & PCI_BASE_ADDRESS_SPACE_IO
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? bus->address_space_io
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: bus->address_space_mem;
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r->size = size;
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r->type = type;
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r->addr = pci_bar_address(dev, region_num, r->type, r->size);
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if (r->addr != PCI_BAR_UNMAPPED) {
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memory_region_add_subregion_overlap(r->address_space,
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r->addr, r->memory, 1);
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}
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}
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static PCIDevice *register_vf(PCIDevice *pf, int devfn, const char *name,
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uint16_t vf_num)
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{
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PCIDevice *dev = pci_new(devfn, name);
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dev->exp.sriov_vf.pf = pf;
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dev->exp.sriov_vf.vf_number = vf_num;
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PCIBus *bus = pci_get_bus(pf);
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Error *local_err = NULL;
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qdev_realize(&dev->qdev, &bus->qbus, &local_err);
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if (local_err) {
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error_report_err(local_err);
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return NULL;
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}
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/* set vid/did according to sr/iov spec - they are not used */
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pci_config_set_vendor_id(dev->config, 0xffff);
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pci_config_set_device_id(dev->config, 0xffff);
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return dev;
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}
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static void register_vfs(PCIDevice *dev)
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{
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uint16_t num_vfs;
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uint16_t i;
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uint16_t sriov_cap = dev->exp.sriov_cap;
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uint16_t vf_offset =
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pci_get_word(dev->config + sriov_cap + PCI_SRIOV_VF_OFFSET);
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uint16_t vf_stride =
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pci_get_word(dev->config + sriov_cap + PCI_SRIOV_VF_STRIDE);
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int32_t devfn = dev->devfn + vf_offset;
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assert(sriov_cap > 0);
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num_vfs = pci_get_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF);
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dev->exp.sriov_pf.vf = g_malloc(sizeof(PCIDevice *) * num_vfs);
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assert(dev->exp.sriov_pf.vf);
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trace_sriov_register_vfs(dev->name, PCI_SLOT(dev->devfn),
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PCI_FUNC(dev->devfn), num_vfs);
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for (i = 0; i < num_vfs; i++) {
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dev->exp.sriov_pf.vf[i] = register_vf(dev, devfn,
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dev->exp.sriov_pf.vfname, i);
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if (!dev->exp.sriov_pf.vf[i]) {
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num_vfs = i;
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break;
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}
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devfn += vf_stride;
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}
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dev->exp.sriov_pf.num_vfs = num_vfs;
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}
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static void unregister_vfs(PCIDevice *dev)
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{
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Error *local_err = NULL;
|
||||
uint16_t num_vfs = dev->exp.sriov_pf.num_vfs;
|
||||
uint16_t i;
|
||||
|
||||
trace_sriov_unregister_vfs(dev->name, PCI_SLOT(dev->devfn),
|
||||
PCI_FUNC(dev->devfn), num_vfs);
|
||||
for (i = 0; i < num_vfs; i++) {
|
||||
PCIDevice *vf = dev->exp.sriov_pf.vf[i];
|
||||
object_property_set_bool(OBJECT(vf), "realized", false, &local_err);
|
||||
if (local_err) {
|
||||
fprintf(stderr, "Failed to unplug: %s\n",
|
||||
error_get_pretty(local_err));
|
||||
error_free(local_err);
|
||||
}
|
||||
object_unparent(OBJECT(vf));
|
||||
}
|
||||
g_free(dev->exp.sriov_pf.vf);
|
||||
dev->exp.sriov_pf.vf = NULL;
|
||||
dev->exp.sriov_pf.num_vfs = 0;
|
||||
pci_set_word(dev->config + dev->exp.sriov_cap + PCI_SRIOV_NUM_VF, 0);
|
||||
}
|
||||
|
||||
void pcie_sriov_config_write(PCIDevice *dev, uint32_t address,
|
||||
uint32_t val, int len)
|
||||
{
|
||||
uint32_t off;
|
||||
uint16_t sriov_cap = dev->exp.sriov_cap;
|
||||
|
||||
if (!sriov_cap || address < sriov_cap) {
|
||||
return;
|
||||
}
|
||||
off = address - sriov_cap;
|
||||
if (off >= PCI_EXT_CAP_SRIOV_SIZEOF) {
|
||||
return;
|
||||
}
|
||||
|
||||
trace_sriov_config_write(dev->name, PCI_SLOT(dev->devfn),
|
||||
PCI_FUNC(dev->devfn), off, val, len);
|
||||
|
||||
if (range_covers_byte(off, len, PCI_SRIOV_CTRL)) {
|
||||
if (dev->exp.sriov_pf.num_vfs) {
|
||||
if (!(val & PCI_SRIOV_CTRL_VFE)) {
|
||||
unregister_vfs(dev);
|
||||
}
|
||||
} else {
|
||||
if (val & PCI_SRIOV_CTRL_VFE) {
|
||||
register_vfs(dev);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Reset SR/IOV VF Enable bit to trigger an unregister of all VFs */
|
||||
void pcie_sriov_pf_disable_vfs(PCIDevice *dev)
|
||||
{
|
||||
uint16_t sriov_cap = dev->exp.sriov_cap;
|
||||
if (sriov_cap) {
|
||||
uint32_t val = pci_get_byte(dev->config + sriov_cap + PCI_SRIOV_CTRL);
|
||||
if (val & PCI_SRIOV_CTRL_VFE) {
|
||||
val &= ~PCI_SRIOV_CTRL_VFE;
|
||||
pcie_sriov_config_write(dev, sriov_cap + PCI_SRIOV_CTRL, val, 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Add optional supported page sizes to the mask of supported page sizes */
|
||||
void pcie_sriov_pf_add_sup_pgsize(PCIDevice *dev, uint16_t opt_sup_pgsize)
|
||||
{
|
||||
uint8_t *cfg = dev->config + dev->exp.sriov_cap;
|
||||
uint8_t *wmask = dev->wmask + dev->exp.sriov_cap;
|
||||
|
||||
uint16_t sup_pgsize = pci_get_word(cfg + PCI_SRIOV_SUP_PGSIZE);
|
||||
|
||||
sup_pgsize |= opt_sup_pgsize;
|
||||
|
||||
/*
|
||||
* Make sure the new bits are set, and that system page size
|
||||
* also can be set to any of the new values according to spec:
|
||||
*/
|
||||
pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, sup_pgsize);
|
||||
pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, sup_pgsize);
|
||||
}
|
||||
|
||||
|
||||
uint16_t pcie_sriov_vf_number(PCIDevice *dev)
|
||||
{
|
||||
assert(pci_is_vf(dev));
|
||||
return dev->exp.sriov_vf.vf_number;
|
||||
}
|
||||
|
||||
|
||||
PCIDevice *pcie_sriov_get_pf(PCIDevice *dev)
|
||||
{
|
||||
return dev->exp.sriov_vf.pf;
|
||||
}
|
|
@ -10,3 +10,8 @@ pci_cfg_write(const char *dev, uint32_t bus, uint32_t slot, uint32_t func, unsig
|
|||
|
||||
# msix.c
|
||||
msix_write_config(char *name, bool enabled, bool masked) "dev %s enabled %d masked %d"
|
||||
|
||||
# hw/pci/pcie_sriov.c
|
||||
sriov_register_vfs(const char *name, int slot, int function, int num_vfs) "%s %02x:%x: creating %d vf devs"
|
||||
sriov_unregister_vfs(const char *name, int slot, int function, int num_vfs) "%s %02x:%x: Unregistering %d vf devs"
|
||||
sriov_config_write(const char *name, int slot, int fun, uint32_t offset, uint32_t val, uint32_t len) "%s %02x:%x: sriov offset 0x%x val 0x%x len %d"
|
||||
|
|
|
@ -7,9 +7,6 @@
|
|||
/* PCI includes legacy ISA access. */
|
||||
#include "hw/isa/isa.h"
|
||||
|
||||
#include "hw/pci/pcie.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
extern bool pci_available;
|
||||
|
||||
/* PCI bus */
|
||||
|
@ -157,6 +154,7 @@ enum {
|
|||
#define QEMU_PCI_VGA_IO_HI_SIZE 0x20
|
||||
|
||||
#include "hw/pci/pci_regs.h"
|
||||
#include "hw/pci/pcie.h"
|
||||
|
||||
/* PCI HEADER_TYPE */
|
||||
#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
|
||||
|
@ -499,6 +497,9 @@ typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
|
|||
AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
|
||||
void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
|
||||
|
||||
pcibus_t pci_bar_address(PCIDevice *d,
|
||||
int reg, uint8_t type, pcibus_t size);
|
||||
|
||||
static inline void
|
||||
pci_set_byte(uint8_t *config, uint8_t val)
|
||||
{
|
||||
|
@ -779,6 +780,11 @@ static inline int pci_is_express_downstream_port(const PCIDevice *d)
|
|||
return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
|
||||
}
|
||||
|
||||
static inline int pci_is_vf(const PCIDevice *d)
|
||||
{
|
||||
return d->exp.sriov_vf.pf != NULL;
|
||||
}
|
||||
|
||||
static inline uint32_t pci_config_size(const PCIDevice *d)
|
||||
{
|
||||
return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
|
||||
|
|
|
@ -24,6 +24,7 @@
|
|||
#include "hw/pci/pci_regs.h"
|
||||
#include "hw/pci/pcie_regs.h"
|
||||
#include "hw/pci/pcie_aer.h"
|
||||
#include "hw/pci/pcie_sriov.h"
|
||||
#include "hw/hotplug.h"
|
||||
|
||||
typedef enum {
|
||||
|
@ -81,6 +82,11 @@ struct PCIExpressDevice {
|
|||
|
||||
/* ACS */
|
||||
uint16_t acs_cap;
|
||||
|
||||
/* SR/IOV */
|
||||
uint16_t sriov_cap;
|
||||
PCIESriovPF sriov_pf;
|
||||
PCIESriovVF sriov_vf;
|
||||
};
|
||||
|
||||
#define COMPAT_PROP_PCP "power_controller_present"
|
||||
|
|
71
include/hw/pci/pcie_sriov.h
Normal file
71
include/hw/pci/pcie_sriov.h
Normal file
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* pcie_sriov.h:
|
||||
*
|
||||
* Implementation of SR/IOV emulation support.
|
||||
*
|
||||
* Copyright (c) 2015 Knut Omang <knut.omang@oracle.com>
|
||||
*
|
||||
* This work is licensed under the terms of the GNU GPL, version 2 or later.
|
||||
* See the COPYING file in the top-level directory.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef QEMU_PCIE_SRIOV_H
|
||||
#define QEMU_PCIE_SRIOV_H
|
||||
|
||||
struct PCIESriovPF {
|
||||
uint16_t num_vfs; /* Number of virtual functions created */
|
||||
uint8_t vf_bar_type[PCI_NUM_REGIONS]; /* Store type for each VF bar */
|
||||
const char *vfname; /* Reference to the device type used for the VFs */
|
||||
PCIDevice **vf; /* Pointer to an array of num_vfs VF devices */
|
||||
};
|
||||
|
||||
struct PCIESriovVF {
|
||||
PCIDevice *pf; /* Pointer back to owner physical function */
|
||||
uint16_t vf_number; /* Logical VF number of this function */
|
||||
};
|
||||
|
||||
void pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset,
|
||||
const char *vfname, uint16_t vf_dev_id,
|
||||
uint16_t init_vfs, uint16_t total_vfs,
|
||||
uint16_t vf_offset, uint16_t vf_stride);
|
||||
void pcie_sriov_pf_exit(PCIDevice *dev);
|
||||
|
||||
/* Set up a VF bar in the SR/IOV bar area */
|
||||
void pcie_sriov_pf_init_vf_bar(PCIDevice *dev, int region_num,
|
||||
uint8_t type, dma_addr_t size);
|
||||
|
||||
/* Instantiate a bar for a VF */
|
||||
void pcie_sriov_vf_register_bar(PCIDevice *dev, int region_num,
|
||||
MemoryRegion *memory);
|
||||
|
||||
/*
|
||||
* Default (minimal) page size support values
|
||||
* as required by the SR/IOV standard:
|
||||
* 0x553 << 12 = 0x553000 = 4K + 8K + 64K + 256K + 1M + 4M
|
||||
*/
|
||||
#define SRIOV_SUP_PGSIZE_MINREQ 0x553
|
||||
|
||||
/*
|
||||
* Optionally add supported page sizes to the mask of supported page sizes
|
||||
* Page size values are interpreted as opt_sup_pgsize << 12.
|
||||
*/
|
||||
void pcie_sriov_pf_add_sup_pgsize(PCIDevice *dev, uint16_t opt_sup_pgsize);
|
||||
|
||||
/* SR/IOV capability config write handler */
|
||||
void pcie_sriov_config_write(PCIDevice *dev, uint32_t address,
|
||||
uint32_t val, int len);
|
||||
|
||||
/* Reset SR/IOV VF Enable bit to unregister all VFs */
|
||||
void pcie_sriov_pf_disable_vfs(PCIDevice *dev);
|
||||
|
||||
/* Get logical VF number of a VF - only valid for VFs */
|
||||
uint16_t pcie_sriov_vf_number(PCIDevice *dev);
|
||||
|
||||
/*
|
||||
* Get the physical function that owns this VF.
|
||||
* Returns NULL if dev is not a virtual function
|
||||
*/
|
||||
PCIDevice *pcie_sriov_get_pf(PCIDevice *dev);
|
||||
|
||||
#endif /* QEMU_PCIE_SRIOV_H */
|
|
@ -86,6 +86,8 @@ typedef struct PCIDevice PCIDevice;
|
|||
typedef struct PCIEAERErr PCIEAERErr;
|
||||
typedef struct PCIEAERLog PCIEAERLog;
|
||||
typedef struct PCIEAERMsg PCIEAERMsg;
|
||||
typedef struct PCIESriovPF PCIESriovPF;
|
||||
typedef struct PCIESriovVF PCIESriovVF;
|
||||
typedef struct PCIEPort PCIEPort;
|
||||
typedef struct PCIESlot PCIESlot;
|
||||
typedef struct PCIExpressDevice PCIExpressDevice;
|
||||
|
|
Loading…
Reference in a new issue