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tcg/tci: Clean up deposit operations
Use the correct set of asserts during code generation. We do not require the first input to overlap the output; the existing interpreter already supported that. Split out tci_args_rrrbb in the translator. Use the deposit32/64 functions rather than inline expansion. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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cbe871313e
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33
tcg/tci.c
33
tcg/tci.c
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@ -168,6 +168,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
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* tci_args_<arguments>
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* where arguments is a sequence of
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*
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* b = immediate (bit position)
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* c = condition (TCGCond)
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* i = immediate (uint32_t)
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* I = immediate (tcg_target_ulong)
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@ -238,6 +239,16 @@ static void tci_args_rrrc(const uint8_t **tb_ptr,
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*c3 = tci_read_b(tb_ptr);
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}
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static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
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TCGReg *r2, uint8_t *i3, uint8_t *i4)
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{
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*r0 = tci_read_r(tb_ptr);
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*r1 = tci_read_r(tb_ptr);
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*r2 = tci_read_r(tb_ptr);
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*i3 = tci_read_b(tb_ptr);
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*i4 = tci_read_b(tb_ptr);
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}
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#if TCG_TARGET_REG_BITS == 32
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static void tci_args_rrrr(const uint8_t **tb_ptr,
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TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3)
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@ -434,11 +445,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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TCGReg r0, r1, r2;
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tcg_target_ulong t0;
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tcg_target_ulong t1;
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tcg_target_ulong t2;
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TCGCond condition;
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target_ulong taddr;
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uint8_t tmp8;
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uint16_t tmp16;
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uint8_t pos, len;
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uint32_t tmp32;
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uint64_t tmp64;
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#if TCG_TARGET_REG_BITS == 32
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@ -629,13 +638,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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#endif
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#if TCG_TARGET_HAS_deposit_i32
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case INDEX_op_deposit_i32:
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tmp16 = *tb_ptr++;
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tmp8 = *tb_ptr++;
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tmp32 = (((1 << tmp8) - 1) << tmp16);
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tci_write_reg(regs, t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32));
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tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len);
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regs[r0] = deposit32(regs[r1], pos, len, regs[r2]);
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break;
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#endif
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case INDEX_op_brcond_i32:
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@ -791,13 +795,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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#endif
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#if TCG_TARGET_HAS_deposit_i64
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case INDEX_op_deposit_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tmp16 = *tb_ptr++;
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tmp8 = *tb_ptr++;
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tmp64 = (((1ULL << tmp8) - 1) << tmp16);
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tci_write_reg(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64));
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tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len);
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regs[r0] = deposit64(regs[r1], pos, len, regs[r2]);
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break;
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#endif
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case INDEX_op_brcond_i64:
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@ -13,7 +13,6 @@ C_O0_I2(r, r)
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C_O0_I3(r, r, r)
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C_O0_I4(r, r, r, r)
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C_O1_I1(r, r)
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C_O1_I2(r, 0, r)
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C_O1_I2(r, r, r)
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C_O1_I4(r, r, r, r, r)
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C_O2_I1(r, r, r)
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@ -126,11 +126,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
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case INDEX_op_rotr_i64:
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case INDEX_op_setcond_i32:
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case INDEX_op_setcond_i64:
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return C_O1_I2(r, r, r);
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case INDEX_op_deposit_i32:
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case INDEX_op_deposit_i64:
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return C_O1_I2(r, 0, r);
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return C_O1_I2(r, r, r);
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case INDEX_op_brcond_i32:
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case INDEX_op_brcond_i64:
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@ -480,13 +478,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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break;
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CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */
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{
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TCGArg pos = args[3], len = args[4];
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TCGArg max = opc == INDEX_op_deposit_i32 ? 32 : 64;
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tcg_debug_assert(pos < max);
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tcg_debug_assert(pos + len <= max);
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tcg_out_r(s, args[0]);
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tcg_out_r(s, args[1]);
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tcg_out_r(s, args[2]);
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tcg_debug_assert(args[3] <= UINT8_MAX);
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tcg_out8(s, args[3]);
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tcg_debug_assert(args[4] <= UINT8_MAX);
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tcg_out8(s, args[4]);
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tcg_out8(s, pos);
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tcg_out8(s, len);
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}
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break;
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CASE_32_64(brcond)
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