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hw/arm/exynos4210: Put external GIC into state struct

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Switch the creation of the external GIC to the new-style "embedded in
state struct" approach, so we can easily refer to the object
elsewhere during realize.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-9-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2022-04-04 16:46:48 +01:00
parent 93afe073df
commit 78cb12a92c
5 changed files with 53 additions and 21 deletions
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2
MAINTAINERS
View file

@ -648,7 +648,7 @@ M: Peter Maydell <peter.maydell@linaro.org>
L: qemu-arm@nongnu.org
S: Odd Fixes
F: hw/*/exynos*
F: include/hw/arm/exynos4210.h
F: include/hw/*/exynos*
Calxeda Highbank
M: Rob Herring <robh@kernel.org>

10
hw/arm/exynos4210.c
View file

@ -455,10 +455,9 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
/* External GIC */
dev = qdev_new("exynos4210.gic");
qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
qdev_prop_set_uint32(DEVICE(&s->ext_gic), "num-cpu", EXYNOS4210_NCPUS);
busdev = SYS_BUS_DEVICE(&s->ext_gic);
sysbus_realize(busdev, &error_fatal);
/* Map CPU interface */
sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
/* Map Distributer interface */
@ -468,7 +467,7 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
}
for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->ext_gic), n);
}
/* Internal Interrupt Combiner */
@ -686,6 +685,7 @@ static void exynos4210_init(Object *obj)
}
object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC);
}
static void exynos4210_class_init(ObjectClass *klass, void *data)

17
hw/intc/exynos4210_gic.c
View file

@ -27,6 +27,7 @@
#include "qemu/module.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/intc/exynos4210_gic.h"
#include "hw/arm/exynos4210.h"
#include "qom/object.h"
@ -44,20 +45,6 @@
#define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100
#define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
struct Exynos4210GicState {
SysBusDevice parent_obj;
MemoryRegion cpu_container;
MemoryRegion dist_container;
MemoryRegion cpu_alias[EXYNOS4210_NCPUS];
MemoryRegion dist_alias[EXYNOS4210_NCPUS];
uint32_t num_cpu;
DeviceState *gic;
};
static void exynos4210_gic_set_irq(void *opaque, int irq, int level)
{
Exynos4210GicState *s = (Exynos4210GicState *)opaque;
@ -100,7 +87,7 @@ static void exynos4210_gic_realize(DeviceState *dev, Error **errp)
* enough room for the cpu numbers. gcc 9.2.1 on 32-bit x86
* doesn't figure this out, otherwise and gives spurious warnings.
*/
assert(n <= EXYNOS4210_NCPUS);
assert(n <= EXYNOS4210_GIC_NCPUS);
for (i = 0; i < n; i++) {
/* Map CPU interface per SMP Core */
sprintf(cpu_alias_name, "%s%x", cpu_prefix, i);

2
include/hw/arm/exynos4210.h
View file

@ -27,6 +27,7 @@
#include "hw/or-irq.h"
#include "hw/sysbus.h"
#include "hw/cpu/a9mpcore.h"
#include "hw/intc/exynos4210_gic.h"
#include "target/arm/cpu-qom.h"
#include "qom/object.h"
@ -103,6 +104,7 @@ struct Exynos4210State {
qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
A9MPPrivState a9mpcore;
Exynos4210GicState ext_gic;
};
#define TYPE_EXYNOS4210_SOC "exynos4210"

43
include/hw/intc/exynos4210_gic.h Normal file
View file

@ -0,0 +1,43 @@
/*
* Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c
*
* Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
* All rights reserved.
*
* Evgeny Voevodin <e.voevodin@samsung.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_INTC_EXYNOS4210_GIC_H
#define HW_INTC_EXYNOS4210_GIC_H
#include "hw/sysbus.h"
#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
#define EXYNOS4210_GIC_NCPUS 2
struct Exynos4210GicState {
SysBusDevice parent_obj;
MemoryRegion cpu_container;
MemoryRegion dist_container;
MemoryRegion cpu_alias[EXYNOS4210_GIC_NCPUS];
MemoryRegion dist_alias[EXYNOS4210_GIC_NCPUS];
uint32_t num_cpu;
DeviceState *gic;
};
#endif