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tcg/sparc: Split out target constraints to tcg-target-con-str.h
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
c947deb13e
commit
77f268e80b
23
tcg/sparc/tcg-target-con-str.h
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23
tcg/sparc/tcg-target-con-str.h
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@ -0,0 +1,23 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Define Sparc target-specific operand constraints.
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* Copyright (c) 2021 Linaro
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*/
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/*
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* Define constraint letters for register sets:
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* REGS(letter, register_mask)
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*/
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REGS('r', ALL_GENERAL_REGS)
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REGS('R', ALL_GENERAL_REGS64)
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REGS('s', ALL_QLDST_REGS)
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REGS('S', ALL_QLDST_REGS64)
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REGS('A', TARGET_LONG_BITS == 64 ? ALL_QLDST_REGS64 : ALL_QLDST_REGS)
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/*
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* Define constraint letters for constants:
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* CONST(letter, TCG_CT_CONST_* bit set)
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*/
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CONST('I', TCG_CT_CONST_S11)
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CONST('J', TCG_CT_CONST_S13)
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CONST('Z', TCG_CT_CONST_ZERO)
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@ -67,18 +67,38 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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# define SPARC64 0
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#endif
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/* Note that sparcv8plus can only hold 64 bit quantities in %g and %o
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registers. These are saved manually by the kernel in full 64-bit
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slots. The %i and %l registers are saved by the register window
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mechanism, which only allocates space for 32 bits. Given that this
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window spill/fill can happen on any signal, we must consider the
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high bits of the %i and %l registers garbage at all times. */
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#if SPARC64
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# define ALL_64 0xffffffffu
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#define TCG_CT_CONST_S11 0x100
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#define TCG_CT_CONST_S13 0x200
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#define TCG_CT_CONST_ZERO 0x400
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/*
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* For softmmu, we need to avoid conflicts with the first 3
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* argument registers to perform the tlb lookup, and to call
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* the helper function.
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*/
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#ifdef CONFIG_SOFTMMU
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#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_O0, 3)
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#else
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# define ALL_64 0xffffu
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#define SOFTMMU_RESERVE_REGS 0
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#endif
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/*
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* Note that sparcv8plus can only hold 64 bit quantities in %g and %o
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* registers. These are saved manually by the kernel in full 64-bit
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* slots. The %i and %l registers are saved by the register window
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* mechanism, which only allocates space for 32 bits. Given that this
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* window spill/fill can happen on any signal, we must consider the
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* high bits of the %i and %l registers garbage at all times.
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*/
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#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
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#if SPARC64
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# define ALL_GENERAL_REGS64 ALL_GENERAL_REGS
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#else
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# define ALL_GENERAL_REGS64 MAKE_64BIT_MASK(0, 16)
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#endif
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#define ALL_QLDST_REGS (ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
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#define ALL_QLDST_REGS64 (ALL_GENERAL_REGS64 & ~SOFTMMU_RESERVE_REGS)
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/* Define some temporary registers. T2 is used for constant generation. */
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#define TCG_REG_T1 TCG_REG_G1
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#define TCG_REG_T2 TCG_REG_O7
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@ -320,45 +340,6 @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
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return true;
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}
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/* parse target specific constraints */
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static const char *target_parse_constraint(TCGArgConstraint *ct,
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const char *ct_str, TCGType type)
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{
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switch (*ct_str++) {
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case 'r':
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ct->regs = 0xffffffff;
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break;
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case 'R':
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ct->regs = ALL_64;
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break;
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case 'A': /* qemu_ld/st address constraint */
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ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
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reserve_helpers:
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tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
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tcg_regset_reset_reg(ct->regs, TCG_REG_O1);
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tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
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break;
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case 's': /* qemu_st data 32-bit constraint */
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ct->regs = 0xffffffff;
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goto reserve_helpers;
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case 'S': /* qemu_st data 64-bit constraint */
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ct->regs = ALL_64;
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goto reserve_helpers;
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case 'I':
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ct->ct |= TCG_CT_CONST_S11;
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break;
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case 'J':
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ct->ct |= TCG_CT_CONST_S13;
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break;
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case 'Z':
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ct->ct |= TCG_CT_CONST_ZERO;
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break;
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default:
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return NULL;
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}
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return ct_str;
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}
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/* test if a constant matches the constraint */
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static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
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const TCGArgConstraint *arg_ct)
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@ -1746,8 +1727,8 @@ static void tcg_target_init(TCGContext *s)
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}
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#endif
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tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
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tcg_target_available_regs[TCG_TYPE_I64] = ALL_64;
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tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
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tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS64;
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tcg_target_call_clobber_regs = 0;
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tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G1);
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@ -66,10 +66,6 @@ typedef enum {
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TCG_REG_I7,
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} TCGReg;
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#define TCG_CT_CONST_S11 0x100
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#define TCG_CT_CONST_S13 0x200
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#define TCG_CT_CONST_ZERO 0x400
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/* used for function call generation */
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#define TCG_REG_CALL_STACK TCG_REG_O6
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@ -172,5 +168,6 @@ extern bool use_vis3_instructions;
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void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
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#define TCG_TARGET_NEED_POOL_LABELS
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#define TCG_TARGET_CON_STR_H
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#endif
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