system/qemu
system/qemu
1
0
Fork 0
mirror of https://gitlab.com/qemu-project/qemu synced 2024-09-06 01:43:39 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/riscv: Add 'P1P13' bit in SMSTATEEN0

Browse source 
Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in
mstateen0 that controls access to the hedeleg.

Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liwei1518@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240606135454.119186-4-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Fea.Wang 2024-06-06 21:54:51 +08:00 committed by Alistair Francis
parent 0c2d5f7396
commit 7750e10656
2 changed files with 9 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
target/riscv/cpu_bits.h
View file

@ -315,6 +315,7 @@
#define SMSTATEEN0_CS (1ULL << 0)
#define SMSTATEEN0_FCSR (1ULL << 1)
#define SMSTATEEN0_JVT (1ULL << 2)
#define SMSTATEEN0_P1P13 (1ULL << 56)
#define SMSTATEEN0_HSCONTXT (1ULL << 57)
#define SMSTATEEN0_IMSIC (1ULL << 58)
#define SMSTATEEN0_AIA (1ULL << 59)

8
target/riscv/csr.c
View file

@ -2252,6 +2252,10 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
wr_mask |= SMSTATEEN0_FCSR;
}
if (env->priv_ver >= PRIV_VERSION_1_13_0) {
wr_mask |= SMSTATEEN0_P1P13;
}
return write_mstateen(env, csrno, wr_mask, new_val);
}
@ -2287,6 +2291,10 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
{
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
if (env->priv_ver >= PRIV_VERSION_1_13_0) {
wr_mask |= SMSTATEEN0_P1P13;
}
return write_mstateenh(env, csrno, wr_mask, new_val);
}